Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. JSTS 2023-06(Vol.23 No.03)
XML PDF INFO REF
Title A Digital FLL-based Sub-harmonically Injection-locked PLL with Resolution-multiplied TDC for Frequency Offset Cancellation
Authors (Jongchan An) ; (Seung-Myeong Yu) ; (Junwon Jeong) ; (Junyoung Song)
DOI https://doi.org/10.5573/JSTS.2023.23.3.202
Page pp.202-205
ISSN 1598-1657
Keywords Injection-locking; digital FLL; time-to-digital-converter; wireline communication
Abstract This paper presents the implementation of a Resolution-Multiplied Time-to-Digital Converter (RM-TDC) and a Sub-harmonically Injection locked Phase-Locked Loop (SIPLL) based on a digital frequency loop to correct frequency offset. The proposed design performs frequency adjustment via a Sampled-Edge-Direction-Dependent Frequency Detector (SEDD-FD), achieving faster and more efficient frequency lock. Also, RM-TDC was used to detect the frequency offset in order to enhance jitter performance. This design has an integrated jitter of 676 fs, a phase noise of -114.26 dBc/Hz at 10 Mhz, occupies an area of 0.052 mm2, and consumes 2.43 mW. It is manufactured using a 65 nm CMOS process.