I. INTRODUCTION

A SIPLL has been proposed as an efficient solution for a low-phase-noise clock generator with a compact area. In modern SoCs, fast locking time is a requirement for the clock generator to reduce the frequency switching time during dynamic frequency scaling. A previously proposed SIPLL ^[1], which employed subsampling to improve jitter performance, had the drawback of being ineffective against PVT and slow lock time. Also ^[2], with low phase noise in a self-calibrated approach, has the disadvantage of consuming a lot of power. ^[3-5] are structures that ensure stability, accurate injection timing, and resistance to PVT but have the disadvantages of large size and complicated hardware. To overcome these shortcomings of the SIPLL, a digital FLL-based SIPLL is proposed with SEDD-FD and Frequency Offset Calibration (FOC) using the RM-TDC.

II. ARCHITECTURE

Fig. 1 shows the overall architecture of the proposed SIPLL. The frequency of the ring oscillator is adjusted by the Digital Frequency Locked Loop (DFLL), and the frequency offset is detected and cancelled by the FOC loop. In the lock-state, the frequency of DIV$_{\mathrm{CK}}$, f$_{\mathrm{DIV}}$, is set to twice that of REF$_{\mathrm{CK}}$, f$_{\mathrm{REF}}$. The SEDD-FD detects the current frequency and generates a MODE signal that determines the mode of the UP/DN counter. The pulse generator outputs Pul$_{\mathrm{inj,r}}$ and Pul$_{\mathrm{inj,f}}$, which are generated at the rising and falling edges of REF$_{\mathrm{CK}}$, respectively. Pul$_{\mathrm{inj,r}}$ is directly injected into the VCO, and Pul$_{\mathrm{inj,f}}$ is used to detect the frequency offset. After LD$_{\mathrm{Fre}}$ is turned on, the RM-TDC starts detecting the phase difference between OUT$_{\mathrm{CK}}$ and Pul$_{\mathrm{inj,r}}$. Then, the phase difference between OUT$_{\mathrm{CK}}$ and Pul$_{\mathrm{inj,f}}$ is detected. The detection results are compared in the offset canceller, and the output of the offset canceller is fed to the current steering type conventional DAC. Because the phase of OUT$_{\mathrm{CK}}$ is decided by Pul$_{\mathrm{inj,r}}$ without any additional phase control loop, the injection timing is automatically adjusted, and stability issues are solved.

Fig. 1. The proposed SIPLL with a digital FLL and frequency offset cancelation.

III. CIRCUIT DESCRIPTION

1. DFLL using SEDD-FD

Fig. 2 shows the flow chart of the SIPLL. The synthesized SEDD-FD controls the operating flow of the DFLL, and the synthesized offset canceller controls the FOC. REF$_{\mathrm{CK}}$ is sampled by the rising and falling edges of DIV$_{\mathrm{CK}}$, and the results are saved to S[0:3]. If S[0:3] matches with 0011, 1100, 1001 or 0110, the UP/DN counter stops and starts to increase the output of the 12-bit counter in the SEDD-FE. The unlock state is detected while the phase of DIV$_{\mathrm{CK}}$ is moved because of the frequency mismatch, and the operation of the DFLL finishes if the output of the 12-bit counter reaches the maximum value. As shown in the timing diagram of the SEDD-FD, if f$_{\mathrm{REF}}$ is faster than half of f$_{\mathrm{DIV}}$, the direction of the rising edges from S^[3] to S^[0] changes from left to right. Conversely, if f$_{\mathrm{REF}}$ is slower than f$_{\mathrm{DIV}}$/2, the direction is opposite. This direction is detected by the SEDD-FD, and the direction is fixed until the frequency state changes. Because of this characteristic, f$_{\mathrm{DIV}}$ monotonically changes until it reaches the target frequency, and this operation reduces the frequency locking time.

Fig. 2. Flow chart of the SIPLL, and block and timing diagrams of the proposed SEDD-FD.

2. Frequency Offset Cancelation (FOC)

Detailed timing diagram of the FOC is shown in Fig. 3. In the lock state, the phase difference between Pul$_{\mathrm{inj,r}}$ and the following edge of OUT$_{\mathrm{CK}}$, t$_{\mathrm{diff,r}}$, matches that between Pul$_{\mathrm{inj,f}}$ and the following edge of OUT$_{\mathrm{CK}}$, t$_{\mathrm{diff,f}}$. If OUT$_{\mathrm{CK}}$ is slower than the target frequency, t$_{\mathrm{diff,f}}$ is larger than t$_{\mathrm{diff,r}}$, and the difference is 0.5N/f$_{\mathrm{offset}}$. In contrast, if OUT$_{\mathrm{CK}}$ is faster than the target frequency, t$_{\mathrm{diff,f}}$ becomes t$_{\mathrm{diff,r}}$ - 0.5N/f$_{\mathrm{offset}}$. As a result, the frequency mismatch is multiplied by N/2, and the actual resolution of the RM-TDC is multiplied by as much as N/2 with the help of the FOC. The following edges after Pul$_{\mathrm{inj,r}}$ or Pul$_{\mathrm{inj,f}}$ could be either a rising or a falling edge due to the operating condition. Therefore, TDC$_{\mathrm{r}}$ and TDC$_{\mathrm{f}}$ are processed in the offset canceller to find the difference between TDC$_{\mathrm{r}}$ and TDC$_{\mathrm{f}}$, unrelated to the following edges. In the case of TDC with sub-ps resolution or the 1-bit TDC, random noise might be detected by the TDC, and the unwanted noise information is included in the detected phase difference. However, in the FOC, because the noise information is not multiplied, it can be filtered by the relatively large resolution of the RM-TDC. Also, the mismatch between the RM-TDC cells can be filtered. Therefore, only the phase difference is detected, and it can cancel the frequency offset.

Fig. 3. Timing diagram of the proposed FOC with RM-TDC.

IV. MEASUREMENT RESULTS

The proposed SIPLL is fabricated in a 65 nm CMOS process, and the active area is 0.052 mm$^{2}$ as shown in Fig. 4. The measured phase noise at 3.6 GHz is presented in Fig. 5, using a 200 MHz reference clock with a fixed duty cycle of 50${\pm}$1\% during the measurement, which is critical in FOC. Before the injection pulse is applied to the VCO, the frequency mismatch is less than 1 MHz due to the FOC. However, as shown in Fig. 5, the in-band noise at 100 kHz without injection locking is -67.44 dBc/Hz because of the FLL characteristic. The in-band noise at 100 kHz with injection locking improves to -103.86 dBc/Hz. Also, the integrated jitter from 100 kHz to 1.8 GHz is 676 fs. The performance of the proposed SIPLL is compared with previous works in Table 1. Compared with previous works which have similar specifications, the proposed SIPLL has smaller occupied area and power consumption. Furthermore, even though the integration range of this work is up to 1.8GHz, the integrated jitter performance and FoM is similar or better.

Fig. 4. Chip microphotograph of the proposed SIPLL.

Fig. 5. Measured phase noises with the proposed digital FLL and SIPLL.

Table 1. Performance comparison

V. CONCLUSIONS

In this article, a DFLL-based SIPLL with RM-TDC for frequency offset cancellation is presented. In order to reduce the frequency lock time, the proposed design took use of the monotonic change in SEDD-FD. Additionally, using the resolution of RM-TDC for filtering, the frequency offset was suppressed. The measured integrated jitter is 676fs$_{\mathrm{RMS}}$ and the phase noise at a 1~MHz is -105.79 dBc/Hz. The proposed SIPLL is fabricated in a 65 nm CMOS process and the active area is 0.052 mm$^{2}$.