| Title |
Resource Analysis on FPGA for Functional Verification of Digital SRAM PIM |
| DOI |
https://doi.org/10.5573/JSTS.2024.24.3.218 |
| Keywords |
FPGA; processing-in-memory; hardware accelerator; neural network; deep learning; SRAM |
| Abstract |
Digital circuits have been usually evaluated on FPGA for the functional verification before the chip design due to the very expensive fabrication cost. However, SRAM-based processing-in-memory array typically activates multiple wordlines, which is different from the operational principle of the conventional SRAMs. When the evaluation of digital circuits is performed in FPGA, SRAMs are replaced by BRAMs, but it is impossible to change the behavior of the BRAMs, which makes it difficult to verify the analog processing-in-memory concepts using FPGAs. In this paper, we analyze the methods to evaluate the digital SRAM processing-in-memory hardware accelerators on FPGA. |