Mobile QR Code QR CODE

  1. (Department of Electronics and Communication Engineering , Hanyang University, 1271 Sa-3 dong ,Sangnok-gu, Ansan, Kyeonggi-do, 425-791, Korea)



Floorplanning, analytical placement, congestion, overlap reduction

I. INTRODUCTION

The floorplanning procedure is to place blocks by using the connection information among the blocks while trying to optimize the wirelength, area utilization, critical path delays, and routing congestions. At the same time, each block should be placed at a legal location without illegal overlaps. During the past few years, several works have been reported for floorplanning optimization. Recently 3D floorplanning techniques are introduced[1,2]. Typical floorplanning methods based on simulated annealing techniques include fixed outline[3] and BSG[4]. Recently, analytical placement methods such as mPL6[5] and APlace3[6] have shown the best performance, for example, in ISPD 2005/2006 placement contests.

An analytical method consists of three stages: global placement, legalization, and post processing. Typically, global placement determines the location of blocks while minimizing the total wirelength and trying to optimize the timing and routability. After global placement, the results may contain macro/cell overlaps, and the macros/cells may not be aligned to the rows. The target of legalization is removing all the overlaps between the macros/cells, and putting all the macros/cells on the rows or columns in the placement area while maintaining the relative positions with minimal displacement. We can obviously find that the overlaps remaining after the global placement directly affect the legalization process and thus the quality of the final solution. Like most analysis methods, mPL6[5] and APlace3[6] regard global placement as a constrained nonlinear optimization problem: They divide the placement area into uniform bins, and seek to minimize the total wirelength under the constraint that the total module area density in every bin is less than or equal to the target density of the bin.

In conventional analytical methods[5,6], the overlaps of the macros/cells are reduced by increasing the global overlap penalty factor in a cost function while iteratively minimizing the cost function using a conjugate gradient method. However, this single global penalty factor may not be effective, since the overlaps in each bin can vary significantly depending on the connectivity of the macros/cells. In this paper, we describe a new adaptive density control method in which the overlaps in each bin are analyzed, and the density of each bin is adaptively determined so that the overlaps can effectively be reduced. Experimental results show that the overlaps before legalization step can be reduced by 90.8 to 98.6% on average when compared to those of the conventional single global penalty factor methods.

In Section II, the overall floorplanning algorithm is described. The new adaptive density control method is explained in detail, in Section III, followed by the description of the experimental results in Section IV. Finally, conclusions are summarized in Section V.

II. OVERALL FLOORPLANNING ALGORITHM

Analytical method is widely used for large scale circuit placement owing to good performance[5,6]. The circuit netlist can be formulated as a hypergraph H={V, E}, where the vertex set, V={v1,v2,…,vn}, represents the set of all macros/cells and the edge set, E={e1, e2,…, en}, represents the set of nets. Analytical placement adopts its own objective function such as that shown in (1) and (2).

(1)
$F(\vec{x}, \vec{y})=W L(\vec{x}, \vec{y})+\sum_{i j}\left(\mu \times P_{d_{i j}}(\vec{x}, \vec{y})\right)$

(2)
$P_{d_{i j}}(\vec{x}, \vec{y})=d_{i j}(\vec{x}, \vec{y})-T D^{2} \quad$ if $\left(d_{i j} > T D\right)$

where $W L(\vec{x}, \vec{y})$ is the total wirelength, $\mu$ is the density penalty factor, $P_{d_{i j}}(\vec{x}, \vec{y})$ is the penalty function to penalize the density violations, $d_{i j}(\vec{x}, \vec{y})$ denotes the density of a bin(i, j), and TD denotes the target density of the bin. Analytical placement allows overlap among the macros/cells and spreads macros/cells by increasing the density penalty factor $\mu$. In the case of the quadratic cost, all the nets are divided into two port nets, and a quadratic wirelength cost model is used. It can find the block position efficiently by using the first order derivative (gradient) of the cost function.

Analytical placement has an advantage in dealing with mixed size circuits. However, it has a disadvantage when there are blocks which should be placed in a restricted area, especially when the available area is highly non-convex. Analytical placement continuously moves blocks with finite resolution and allows overlaps between blocks. Therefore, an analytical method needs a legalization step. The legalization step is to remove all the overlaps between the macros and cells and to put all the macros and cells in the legal placement area. To minimize the disruption of the optimized positions of macros/cells during legalization, the amount of overlaps should be minimized during the global analytical placement.

III. NEW EFFECTIVE ADAPTIVE DENSITY CONTROL FOR OVERLAP REDUCTION

In analytical placement, macros/cells are moved by using their gradients. When two macros/cells are connected by a net, then attractive force is produced due to the connection, and repulsive force is produced due to the overlap penalty term. When the attractive and repulsive force form an equilibrium, the gradient becomes zero until the penalty weight is increased. In conventional analytical method, one global penalty weight is used. We developed a new method in which the cell density for each bin is adaptively adjusted by using the local congestion.

Eqs. ((3), (4)) show the objective function of our analytical method. In our new method, the density daij for each bin (i,j) is adaptively adjusted for effective removal of overlaps

(3)
$F(\vec{x}, \vec{y})=W L(\vec{x}, \vec{y})+\sum_{y}\left(\mu \times P_{d_{i j}}(\vec{x}, \vec{y})\right)$

(4)
$P_{d_{i j}}(\vec{x}, \vec{y})=d a_{i j}(\vec{x}, \vec{y})-T D^{2} \quad$ if $\left(d a_{i j} > T D\right)$

where $P_{d_{i j}}(\vec{x}, \vec{y})$ is the density penalty function to penalize the density violations. Now we explain how the adaptive density for each bin is computed.

1. Local Density Improvement

The conventional analytical method uses a single global density penalty factor value to control cell spreading. With the single global penalty factor, large overlaps appear between the macros/cells with high connectivity. For example, Fig. 1 shows a simple floorplanning results by our adaptive density control (ADC) with 25 same sized macro cells, for simplicity. Each cell is connected with neighbor cells, as shown in Fig. 1(a). Only the center cell of the example has 5 times high connectivity with neighbor cells. The center cell and the neighbor cells have high connectivity and thus produce large overlaps, as shown in Fig. 1(b) when conventional analytical placement is used. These overlaps are due to the strong attractive force due to string connections.

Since all the macros/cells are initially placed near the center of a chip in analytical placement, most of the macros/cells have overlaps. We use the conventional analytical method until the macros/cells are spread so that the total overlaps become less than a fraction (currently 35%) of the total cell area. Then we start to adaptively adjust the bin density for each cell by considering local density to obtain placement result with less overlaps as shown in Fig. 1(c). Algorithm 1 shows the adaptive density control algorithm. In the current implementation, $\rho$ = 0.00049 is used. In the algorithm, when (bin_density > target_density), the adjusted_density is increased at each iteration. Increasing of adjusted_density means increase of repulsive force, to reduce overlaps in congested regions. When (bin_density < target_density) for the bin and all the neighboring bins, the original density becomes the adjusted density. When (bin_density < target_density) for the bin and (bin_density ≥ target_density) for a neighbor bin, then the adjusted_density is slowly reduced by multiplying the bin_density to prevent oscillation in density.

Fig. 1. Comparison of overlaps in results of conventional and our ADC methods (Real simulation results).

../../Resources/ieie/JSTS.2019.19.1.042/fig1.png

2. Bin Grid Resolution Improvement

For more effective and rapid calculation of the density during the analytical process, the entire region is divided into m by n bins, and the density of each bin is computed. However, the density value may not accurately reflect the overlaps in the bin. For example, there is an overlap between cells H and G in Fig. 2, even though the density of the shared bin is lower than the target density. This is because the overlap area is smaller than the empty area in the shaded bin.

Fig. 2. Overlap may exist even when bin_density < target_density due to rigid macro cells.

../../Resources/ieie/JSTS.2019.19.1.042/fig2.png

In order to resolve these problems, due to the limited bin resolution, the adjusted_density is updated by using Algorithm 2. The purpose is to reduce the overlaps, if any, in the bins where the density is less than the target_density.

IV. EXPERIMENTAL RESULTS

We implemented our adaptive density control algorithm in the C++ language on a 3.4 GHz Intel Xeon CPU with 64 GB memory. We used the GSRC hard benchmark to illustrate the performance of our algorithm. The information of the GSRC-hard benchmark is shown in Table 1.

Table 1. GSRC-hard Benchmark

Circuit

Number of modules

Number of nets

Number of pins

n10

10

118

248

n10b

10

133

274

n10c

10

119

246

n30

30

349

723

n30b

30

350

725

n30c

30

390

818

n50

50

485

1050

n50b

50

511

1105

n50c

50

485

1050

n100

100

885

1873

n100b

100

806

1797

n100c

100

855

1830

n200

200

1585

3599

n200b

200

1714

3640

n200c

200

1532

3513

n300

300

1893

4358

We used an analytical method and the conjugate gradient method to solve the unconstrained optimization problem. For this experiment, we implemented a legalization procedure based on [7][7]. When the total

overlap area is less than 35% of total macro/cell area, we apply adaptive density control (shown in Algorithm 1 and 2). The threshold value 35% was experimentally chosen. If this value is too small, the adaptive density control starts too early, when the placement information is not yet accurate, wasting CPU time. When this value is too large, the adaptive density control starts too late and may cause less optimized final results. For the n30 circuit in the GSRC-hard benchmark, the amount of overlaps each global placement iteration without and with our adaptive density control feature is shown in Fig. 3. From the result, one can see that the amount of overlap is reduced very effectively and efficiently with adaptive density control. In the current implementation, $\rho$ = 0.00049 and $\sigma$ = 0.1 are used, since optimal average half-parameter wirelength (HPWL) can be obtained with three values ( $\mu$, $\rho$, $\sigma$ ). These parameters are optimized based on experiments and $\mu$ increased from 1, $\rho$ = 0.00049 and $\sigma$ = 0.1 are used.

Fig. 3. Overlap reduction comparison.

../../Resources/ieie/JSTS.2019.19.1.042/fig3.png

Table 2 shows the results of the GSRC-hard benchmark without and with our adaptive density control feature. The area for floorplanning is fixed for all circuits by 800x800 in Table 2. We also do the experiment by changing the floorplanning area constraint. The area constraint refers to the ratio of the floorplanning area to the sum of the macro/cell area. The experimental results of the different area constraints (140% and 120%) without and with our adaptive density control are shown in Table 3 and Table 4. To the best of our knowledge, there is no previous report which shows effective overlap reduction techniques. Therefore, we compare the results without and with the adaptive density control feature to evaluate the performance. The overlap amount is an area and the displacement is a distance.

Table 2. GSRC-hard Benchmark Results with fixed area (800x800)

Circuit

HPWL Cost

Overlap Amount

Displacement

CPU Time (s)

Before legalization

After legalization

before legalization

Max displacement

Total displacement

Without

With

Without

With

Without

With

Without

With

Without

With

Without

With

n10

49177.5

48302.7

50332.3

48334.8

16326.4

62.4

88.4

3.3

170.0

4.2

35.64

120.13

n10b

58710.8

58546.1

58781.5

58547.1

482.4

8.1

5.4

0.1

13.4

0.4

17.38

155.27

n10c

50173.7

49473.4

51538.3

49518.1

5720.4

412.9

154.9

2.1

396.5

7.6

42.39

56.35

n30

144274.6

144362.1

148100.1

144650.7

12652.1

87.7

205.7

1.4

833.5

8.2

129.58

152.62

n30b

162048.4

160465.5

162248.6

160760.8

135.9

85.5

7.3

4.1

36.1

21.3

58.99

61.80

n30c

189403.7

185497.0

189405.2

185601.1

23.2

256.5

0.2

2.4

0.7

18.3

24.73

62.11

n50

174691.1

168524.8

174793.5

169277.6

88.8

243.4

3.7

3.3

22.5

32.5

49.00

103.55

n50b

211011.0

206343.8

211137.9

207354.8

143.7

192.3

3.8

2.2

24.6

29.4

45.48

174.40

n50c

167689.1

162383.3

167753.1

166042.5

59.7

90.5

2.8

1.8

14.8

17.7

69.14

99.15

n100

275372.0

263357.7

276994.4

270551.9

1803.2

96.9

42.6

28.0

390.7

85.7

92.49

100.49

n100b

292682.9

282307.4

295394.5

292542.0

1337.2

478.8

56.4

58.2

712.3

583.9

79.23

86.53

n100c

271202.6

260705.2

271621.5

266292.3

866.1

212.4

24.5

42.5

115.9

237.1

71.53

171.63

n200

498287.1

429997.8

498960.4

485193.9

535.7

271.7

7.3

6.4

258.0

220.6

58.84

137.23

n200b

504432.8

452002.2

510866.1

502178.8

890.9

530.5

85.3

49.9

1454.3

826.7

111.98

49.72

n200c

473234.5

408141.7

476880.1

473452.0

467.2

489.4

44.6

73.1

626.2

896.1

85.67

99.59

n300

567474.3

472761.3

571521.9

560621.1

666.6

349.1

29.6

10.9

1020.0

420.1

158.17

105.08

Ratio

100%

91.8%

100%

98.2%

100%

9.2%

100%

38.0%

100%

56.0%

100%

153.6%

Table 3. GSRC-hard Benchmark Results with area constraint (140%)

Circuit

HPWL Cost

Overlap Amount

Displacement

CPU Time (s)

Before legalization

After legalization

before legalization

Max displacement

Total displacement

Without

With

Without

With

Without

With

Without

With

Without

With

Without

With

n10

48875.5

47479.3

52216.2

48005.9

35030.9

117.1

112.2

2.9

525.3

7.9

63.39

697.08

n10b

55637.4

62676.4

64083.5

62683.3

81501.7

178.8

200.5

1.6

1163.3

4.6

55.70

66.51

n10c

49455.8

48856.9

50258.3

48861.1

17967.9

118.5

155.0

1.2

160.3

2.1

78.11

68.99

n30

148290.7

146727.3

149059.2

149018.8

8400.5

125.2

56.6

4.6

460.8

16.8

171.09

682.27

n30b

155489.1

156465.2

157212.3

157145.9

9146.8

14.1

79.9

0.2

208.4

1.0

120.06

632.61

n30c

181180.2

181762.3

184683.2

182558.1

8267.7

392.6

76.6

5.5

570.7

48.3

149.43

634.12

n50

173630.6

169760.2

173812.6

172221.5

344.2

73.6

5.6

1.7

51.8

11.8

135.19

439.39

n50b

204646.2

202628.5

210200.4

204627.4

7868.3

126.6

78.2

1.9

1035.1

12.7

135.26

274.38

n50c

165705.0

163105.7

166458.5

166997.9

1908.8

102.1

37.0

3.8

179.6

12.8

198.98

678.93

n100

281594.1

270644.7

283096.5

276518.2

1009.2

85.2

67.9

3.8

320.6

34.3

261.12

141.29

n100b

291592.6

286254.3

292663.2

289597.7

1161.0

123.5

32.0

3.1

252.0

60.0

208.75

187.48

n100c

276151.1

265579.7

276912.4

272557.4

856.0

83.3

22.7

1.5

220.9

21.8

192.20

179.62

n200

498138.3

444927.5

501834.8

505063.8

1587.0

202.6

80.8

54.8

832.9

433.8

222.69

716.50

n200b

502956.9

452054.3

511382.6

499673.7

878.3

172.5

69.2

3.2

1795.0

81.0

180.08

354.21

n200c

463549.9

415629.9

466311.8

464359.4

442.7

154.5

47.0

2.4

459.6

80.5

183.75

302.17

n300

571388.6

475058.6

580309.9

572242.1

1314.3

387.8

73.3

66.7

1987.1

1220.5

254.55

160.04

Ratio

100%

93.2%

100%

98.0%

100%

1.4%

100%

13.3%

100%

20.0%

100%

238.1%

Table 4. GSRC-hard Benchmark Results with area constraint (120%)

Circuit

HPWL Cost

Overlap Amount

Displacement

CPU Time (s)

Before legalization

After legalization

before legalization

Max displacement

Total displacement

Without

With

Without

With

Without

With

Without

With

Without

With

Without

With

n10

50803.6

48311.8

50942.5

48528.8

2071.4

170.2

17.3

2.3

24.5

5.3

237.38

508.66

n10b

55085.0

46753.9

65534.2

64112.9

94810.8

1922.3

236.3

27.8

1055.4

86.0

56.01

769.33

n10c

46915.9

48484.1

50828.5

49722.2

37978.4

4010.2

152.2

43.4

613.3

112.7

126.20

811.70

n30

148862.3

147409.1

150678.0

148076.3

6883.1

743.0

86.5

11.7

294.3

64.8

107.60

815.15

n30b

154121.5

157238.6

159547.4

158102.2

24342.7

1302.4

127.6

23.9

1002.1

39.6

140.76

797.75

n30c

181207.3

180042.8

182618.6

181874.2

11949.6

2666.6

77.2

25.1

340.5

88.4

192.71

822.06

n50

174609.8

174404.9

178748.3

177496.4

8993.1

1717.0

58.8

15.1

785.8

122.2

336.82

810.81

n50b

207750.3

205065.7

210212.6

207689.8

3158.1

288.5

48.8

10.4

326.6

45.3

278.38

736.17

n50c

165485.5

161884.3

169349.4

166024.9

8963.7

2736.0

176.4

33.1

1338.4

273.5

484.38

830.84

n100

276818.3

267236.8

279196.1

277260.6

3027.7

110.5

60.4

3.1

667.1

541.6

359.15

541.57

n100b

295738.3

287193.5

298555.0

294283.7

960.5

249.7

60.5

6.6

587.3

80.0

371.48

707.01

n100c

269201.4

262127.8

281807.1

271703.2

5174.5

86.4

118.4

2.4

2194.3

26.4

226.44

580.64

n200

490078.2

439936.1

500118.8

491822.0

2420.0

362.7

72.3

27.8

1715.1

398.0

372.34

852.19

n200b

501244.1

456288.6

506584.7

501859.0

2071.9

156.2

74.6

39.8

1305.0

307.1

166.49

581.27

n200c

461738.1

416661.5

470136.9

464195.8

1342.2

357.5

79.6

8.1

1539.5

219.3

355.87

786.63

n300

567570.5

478928.2

584336.9

575529.2

4173.1

639.1

112.4

61.7

3667.2

1357.2

252.77

532.28

Ratio

100%

93.3%

100%

98.5%

100%

8.0%

100%

21.9%

100%

21.6%

100.0

282.5%

From Table 2-Table 4, one can see that the overlap before legalization can be reduced by 90.8 to 98.6% on average. The Max displacement (Total displacement) after legalization can also be reduced by 62.0 to 88.3% (44.0 to 85.1%) on average, respectively, when compared to those of the conventional single global penalty function method. The HPWL cost after legalization can also be reduced by 1.5 to 2.0 %. With adaptive density control, the CPU time takes longer (154 to 283%), however, the reduction of the overlaps after analytical placement is significant, and thus the displacement of macros/cells can also be significantly reduced during legalization.

A fixed area of 800x800 is used in Table 2. Therefore, area margin is large for small circuits and margin is small for big circuits. The area constraint 100% means that the area is tight and there is no room to move cells. When area constraints are 120% and 140% of total cell area, there are 20% and 40% margins in area and thus further optimization can be achieved. In Table 2, the overlap amount of some circuits (n30c, n50, n50b, n50c, n200c) are increased. In cases of 120% and 140%, large cells cannot be easily moved since the area margin is not big (only 20% or 40%). On the other hand, the large size cells within the fixed size of 800x800 can move easily even if the proposed method is applied because there are many empty spaces within the boundary. Therefore, the cells spread outward quickly in the fixed area with large margin. At the end, the cells are attracted toward the center to reduce the total wierlength, resulting in slight overlaps, and therefore, the results can be worse in some cases in the fixed area case with large margin.

Table 5 shows GSRC-hard Benchmark Results using the Parquet-4, A-FP and new ADC analytical methods with area constraint (115%). Our method produced 32% and 14% better results in HPWL when compared to a Parquet-4[3] and a A-FP[8].

Table 5. GSRC-hard Benchmark Results using the A-FP and Parquet-4 with area constraint (115%)

Circuit

HPWL Cost

Parquet-4[3]

A-FP[8]

Ours

n100

342103

291628

279082.5

n200

630014

572145

492747.8

n300

770354

702822

573381.7

Table 6 shows the detailed routing results of the GSRChard benchmark for conventional and new ADC analytical methods. To compare the final results after detailed routing, we performed the detailed routing using Synopsys design compiler using 0.18 μm library. Since lef/def data of GSRC benchmarks are not given, we transformed placement results into lef/def format to perform detailed routing. Our method produced 1.5% to 2.0% better final results in wirelength when compared to a conventional analytical method as shown in Table 6(for area constraints of 140% and 120%). This means that our proposal method can improve the final wirelength of the design.

Table 6. GSRC-hard Benchmark Routing Results

Circuit

Wirelength

Area constraint 140%

Area constraint 120%

Without

With

Without

With

n10

62659

57127

63945

58597

n10b

76900

74593

77854

76984

n10c

60310

58145

60584

58645

n30

178871

177332

179846

172021

n30b

188655

187004

188655

187004

n30c

221620

217244

222531

220912

n50

208575

204944

209453

208813

n50b

252240

243507

259765

259038

n50c

199750

198728

200397

191735

n100

339716

329057

341439

340897

n100b

351196

344621

352996

350062

n100c

332295

324343

341642

329741

n200

602202

601026

604193

602095

n200b

613659

594612

617019

603548

n200c

559574

552588

576483

571928

n300

696372

680968

700649

689173

Ratio

100%

98.0%

100%

98.47%

V. CONCLUSIONS

The overlaps remaining after the global placement directly affect the complexity of legalization and the quality of the final floorplaning solution. Most of the conventional analytical methods just control a single global penalty factor while iteratively minimizing the cost function to reduce the overlaps. We have developed an effective adaptive density control method in which the density of each bin is adaptively controlled to reduce the overlaps among the macros/cells while minimizing the total wirelength or other cost function in the global placement stage. The experimental results show that overlaps can be greatly reduced during analytical placement and thus the displacement required during legalization can also be significantly reduced. The final results after detailed routing can also be improved by using the proposed adaptive density control technique.

ACKNOWLEDGMENTS

This research has been supported by Samsung Electronics Co.

REFERENCES

1 
Lin J., Chiu P., Chang Y., 2016, SAINT: Handling Module Folding and Alignment in Fixed-outline Floorplans for 3D ICs, Proc. ICCAD, pp. 1-7DOI
2 
Lin J., Yang J., Nov. 2017, Routability-driven TSV-aware Floorplanning Methodology for Fixed-outline 3D ICs, IEEE Trans. Comput.-Aided Design Circuits Syst., Vol. 36, No. 11, pp. 1856-1868DOI
3 
Adya S. N., Markov I. L., Dec. 2003, Fixed-outline floorplanning: enabling hierarchical design, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 11, No. 6, pp. 1120-1135DOI
4 
Nakatake S., et al , Jun. 1998, Module packing based on the BSG-structure and IC layout applications, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., Vol. 17, No. 6, pp. 519-530DOI
5 
Chan T., et al , 2006, mPL6: Enhanced multilevel mixedsize placement, Proc. ACM ISPD, pp. 212-214DOI
6 
Kahng A. B., Wang Q., 2006, A faster implementation of APlace, Proc. ACM ISPD, pp. 218-220DOI
7 
Wang Y., Yeo D., Shin H., 2013, An Effective Legalization Method Using Iterative Movement of Blocks, Proc. SoCGoogle Search
8 
Zhan Y., Feng Y., Sapatnekar S., 2006, A Fixed-die Floorplanning Algorithm Using an Analytical Approach, Proc. ASP-DAC, pp. 771-776DOI

Author

Donghoon Yeo
../../Resources/ieie/JSTS.2019.19.1.042/au1.png

received the B.S. degree in electrical and computer engineering from Hanyang University, Ansan, Korea, in February 2006.

He received his MS degree in mechatronics engineering from Hanyang University in August 2008.

His research interests include CAD and VLSI system design.

Yu Wang
../../Resources/ieie/JSTS.2019.19.1.042/au2.png

received the B.S. degree in communication engineering from Harbin Institute of Technology, China, in July 2010.

He received his Ph.D. degree in electronics and communication engineering from Hanyang University, Korea, in August 2018.

His research interests include CAD development and machine learning.

Iksoon Lim
../../Resources/ieie/JSTS.2019.19.1.042/au3.png

received the B.S. degree in electrical & communication engineering from Hanyang University, Ansan, Korea, in February 2011.

He received his MS degree in Electronics and communications engineering from Hanyang University in February 2013.

His research interests include VLSI design and CAD.

Hyunchul Shin
../../Resources/ieie/JSTS.2019.19.1.042/au4.png

received the B.S. degree in Electronics Engineering from Seoul National University in 1978, and the MS degree in Electrical Engineering from the Korea Advanced Institute of Science and Technology in 1980. He received the Ph.D. in Electrical Engineering a Computer Sciences from the University of California at Berkeley in 1987.

In 1983, he received a Fullbright scholarship.

From 1987 to 1989, he was a Member of the Technical Staff at AT & T Bell Laboratories, Murray Hill, NJ. Since 1989, he has been a professor with the Division of Electrical Engineering of Hanyang University, Korea.

His current research interests include computer vision and artificial intelligence.