(Jae-Sik Yoon)
1
(Jintae Kim)
1†
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Split-CDAC, digital calibration, successive approximation register ADC, least-squares optimization, sine wave fitting
I. INTRODUCTION
A Successive Approximation Register (SAR) A/D converter (ADC) employing an attenuation
capacitor D/A converter (CDAC) is a popular topology for high resolution SAR ADCs[1-6]. Illustrated in Fig. 1, the attenuation capacitor denoted as Ca, which is also referred to as the bridge capacitor, renders switchable capacitance
in CDAC smaller than the smallest physical unit capacitance, thereby enabling a noise
and power optimized CDAC-based SAR ADC design even for very high resolutions. However,
not only is it impractical to have precise matching between Ca and the capacitance sum of the LSB section of the CDAC, the total parasitic capacitance
at the LSB side of the attenuation capacitor, denoted as CPL in Fig. 1, also degrades overall linearity of the CDAC. The combined challenges demand that
there need be some means to calibrate out this analog inaccuracy when one desires
to use the CDAC with bridge capacitor for a high linearity SAR ADC design.
Fig. 1. Overall architecture of SAR ADC with bridge CDAC utilizing digital-domain
calibration.
There have been quite a few number of papers that have tried to address this problem
from both analog and digital domains. For instance, the analog domain technique described
in [1][1] utilizes an extra CDAC to calibrate ratio mismatch due to parasitic capacitor, which
increases analog circuit complexity. One can also use large attenuation capacitor
to reduce its variation at the cost of larger total capacitance than necessary [2][2]. Several digital domain calibration techniques have also been demonstrated. In [3][3], error voltage for each digital code is measured using dedicated DAC switching scheme
and 32-tap FIR filter, which adds substantial hardware complexity. The method presented
in [4][4] and [5][5] utilizes histogram testing and code density check to obtain desired digital bit weights,
thereby not requiring dedicated hardware to estimate the bit weights for the calibration.
The downside for the histogram method is that it often requires large number of data
samples to calculate bit weight, leading to long calibration time. More recently,
[7][7] demonstrates a method that finds the ideal bit weight of MSB section capacitors as
well as the weight of entire LSB section through a sequence of measurements, but no
silicon verification has been provided.
In this paper, we present an alternative foreground digital-domain method that can
calibrate a SAR ADC with a bridge capacitor. Our method, without using dedicated hardware
for error extraction, finds optimal digital bit weights by solving a least-squares
optimization problem under the framework of convex optimization. As will be presented
in this paper, in comparison to the histogram method, our method is much simpler to
use and works with significantly fewer ADC output samples.
While it has been shown that the least-squares method can calibrate out the CDAC mismatch
in sigma-delta ADC[8], the residue amplifier finite gain in pipelined ADC[9], and the CDAC mismatch in binary-weighted SAR ADC[10], our contribution is to show that under the condition that the bridge capacitance
is oversized than nominal value, the least-squares method can be extended to the calibration
of the CDAC nonlinearity arising from the bridge capacitor. Another contribution is
to provide a detailed hardware implementation of the digital calibration engine that
is suitable for a SAR ADC utilizing asynchronous clocking scheme. We verify the viability
of our method via model-based simulation as well as silicon measurement using a prototype
0.7 V 5 MS/s SAR ADC in 65-nm CMOS process.
Section II reviews the dominant error source in CDAC with a bridge capacitor and describes
a design requirement on the CDAC to embed built-in redundancy, which is followed by
the calibration algorithm based on least-squares minimization. Numerical examples
are provided to show the viability of the presented method. Section III presents implementation
details and measured results of the prototype SAR ADC in 65-nm CMOS process. Section
IV concludes the paper with a brief summary.
II. BRIDGE CDAC CALIBRATION PRINCIPLE
1. Bridge CDAC Error Sources
Fig. 1 displays the overall ADC architecture we consider, where we assume a differential
evenly-split CDAC with top-plate sampling as a representative SAR ADC utilizing bridge
CDAC[11]. For total N+1-bit raw resolution, CDAC is designed to have N-bit resolution given
that the first MSB can be resolved differentially without the CDAC being engaged.
The attenuation capacitor $C_{a}$ splits the DAC into two equal N/2-bit binary CDACs
with unit capacitor $C_{u}$. SAR control logic drives the sequential operation of
the CDAC based on the output of the comparator, providing raw digital output D[N:0]
to the digital calibration engine. The calibrated ADC output is computed as a weighted
sum of raw ADC outputs D[N:0] and optimal digital bit weights w[N:0], i.e.,
In principle, the ideal attenuation capacitor value for the CDAC in Fig. 1 should be chosen as
which can be approximated as $\mathrm{C}_{\mathrm{a}, \mathrm{ideal}} \approx \mathrm{C}_{\mathrm{u}}$
when N is large for an N-bit split-CDAC. With parasitic capacitance $C_{PL}$, however,
the output voltage of CDAC deviates from its ideal value, leading to linearity error
in the overall ADC transfer characteristic. One can show that the output voltage of
CDAC can be expressed as
where $C_{L,tot}$ and $C_{M,tot}$ are total capacitance excluding parasitic capacitance
in LSB and MSB array of CDAC, respectively, and $C_{L}=\sum_{i=0}^{N / 2-i} 2^{i}
\cdot C_{u} \cdot D[i]$ and $\mathrm{C}_{\mathrm{M}}= \sum_{i=0}^{N / 2-i} 2^{j} \cdot
C_{u} \cdot D\left[\frac{N}{2}+j\right]$ are code-dependent capacitance. Our analysis
is in line with previous works[1,3] that analyzed the split-CDAC nonlinearity with some differences in notation.
Eq. (3) indicates that there are two main error sources in split CDAC: total parasitic capacitance
at the LSB side of the bridge capacitor, $C_{PL}$ in Fig. 1, and the error in $C_{L}$ and $C_{M}$ due to the mismatches between unit capacitors.
To correct these errors in the digital domain, redundant DAC analog levels are necessary
to create room for correcting linearity errors in digital post processing. Such a
redundancy can be embedded by using oversized bridge capacitor, i.e., $\mathrm{C}_{\mathrm{a}}=\mathrm{a}
\mathrm{C}_{\mathrm{a}, \mathrm{ideal}}$ with a > 1. Intuitively, the oversized
bridge capacitance increases the total effective capacitance to ground at $V_{out}$.
As a result, when the code changes in the MSB array, the actual DAC voltage step is
smaller than the ideal voltage step, leading to a raw DAC output with non-monotonic
transfer characteristic. In other words, redundant analog levels are purposely embedded
in the CDAC transfer function, which can be utilized in calibrating overall SAR ADC
linearity in digital domain.
Using larger $C_{a}$ increases the amount of redundancy, which is advantageous for
correcting larger errors from non- idealities in CDAC. However, large $C_{a}$ comes
at the cost of smaller effective DAC full-swing, which reduces the effective resolution
of the DAC. Therefore, the oversizing factor α has to be chosen judiciously considering
both the effective resolution and the amount of redundancy for linearity correction.
2. Weight Estimation Via Least-squares Minimization
With the redundancy in place by using oversized bridge capacitor, the prime goal is
then to find out the best set of digital weight coefficients $w$[N : 0] = [$w_{N}$
$w_{N-1}$ $\cdots$ $w_{0}$] for raw digital bits. Many previous research works attempted
to find the digital weight using custom digital hardware[7,12]. In this work, we present a software-based method that is more flexible than using
the hardwired logic. In many commercial products such as high-performance instruments
where the digitaldomain calibration is being used, the ADC co-exists with an embedded
processor and therefore the software-based method has an advantage of re-using existing
hardware resource in finding optimal digital weights.
Fig. 2 illustrates the entire calibration procedure. We inject a sinusoid with known frequency
and unknown phase as a calibration-mode input signal, and corresponding raw ADC output
with record length of $M$ is collected. To find the optimal digital weight, we formulate
a following least-squares minimization problem as
Fig. 2. Flow char of the calibration.
where yi is the estimated sampled sinewave with known frequency $f_{s}$ at time $t_{i}$,
is the $\mathrm{d}_{i}^{\mathrm{T}}$ is the ith row of ADC output matrix $D \in R^{M
\cdot(N+1)}$ whereby element $d_{ij}$ in D is $j$th bit of SAR ADC output corresponding
to $y_{i}$, and $w \in R^{N+1}$ is digital weight vector where each element $w_{i}$
is the optimization variable in the problem. Note that $A_{s}$ and $A_{c}$ are dummy
optimization variables to jointly estimate the magnitude and phase of the input sinewave.
The formulation in (4) is a convex optimization problem, and can be readily solved by using software packages.
In this work, the algorithm in (4) is implemented in MATLAB by utilizing the optimization software package called CVX[13]. Being able to find optimal digital weight by solving a convex optimization brings
many benefits. First, compared to custom-developed methods or histogram testing method,
this method guarantees global optimality of the digital weights, which is inherent
nature of least-squares minimization. Second, the optimization corrects both the unit
capacitor mismatch as well as the linearity error from the parasitics in oversized
bridge capacitor because the optimization problem does not distinguish the type of
error sources; rather, it simply finds the best set of $w_{i}$ that minimizes the
total error in least-squares sense. Note that the calibration using the digital weights
by solving the problem (4) is linear in nature and hence is not able to calibrate the frequencydependent non-linearity;
only unit capacitor mismatch and top-plate parasitic of the bridge capacitor are calibrated.
3. Numerical Experiment
In order to verify the presented calibration method, we created a MATLAB-based behavioral
model of a SAR ADC with a bridge capacitor shown in Fig. 1. We consider a SAR ADC with 6-6 split CDAC with 20% of parasitic capacitance for
the bridge capacitor, i .e. $C_{PL}$ = $0.2 C_{L,tot}$. For the unit capacitors, Gaussian
errors are added assuming standard deviation of $\sigma$=3% for unit capacitance of
$C_{u}$=10fF. To embed redundancy, oversized bridge capacitance of $C_{a}$ = $2C_{a.ideal}$
is used. In order to rule out the impact of noise, no thermal noise has been added
to the model. For SNDR and error calculation, simulated ADC output is analyzed using
IEEE effective-number-of-bits (ENOB) via the timedomain best- fit method[14].
Fig. 3 shows INL of an ADC output against ideal sinewave before and after the calibration.
It is evident that the INL, ranging from -8.3 LSB to 8.3 LSB before the calibration,
reduces drastically down to -0.34 LSB ~ +0.44 LSB after the calibration. In terms
of SNDR, it improves from 41.08 dB to 74.05 dB after the calibration.
Fig. 3. Simulated residual error of SAR ADC using split CDAC with and without calibration.
To further investigate the relationship between SNDR improvement and the amount of
required redundancy in a statistical sense, 1000 Monte Carlo simulations have been
performed for two different values of attenuation capacitance $C_{a}$ = $\alpha \mathrm{C}_{\mathrm{a},
\text { ideal }}$: $\alpha$=1.3 and $\alpha$=1.8, where $\alpha$ = 1 corresponds to
ideal bridge capacitance. Fig. 4(a) shows the distribution of post-calibrated SNDR after the calibration when $\alpha$=1.3.
Due to insufficient redundancy, there is a long tail in the distribution where the
worstcase SNDR can be as low as 63dB. In contrast, with $\alpha$=1.8 for larger redundancy,
all voltage jumps across the code boundary and the post-calibrated SNDR distribution
is narrowly confined between 72.5 dB and 74 dB. It is worth noting that the peak SNDR
is however smaller when using $\alpha$=1.8; this is because larger redundancy range
comes at the cost of DAC full scale reduction, hence the impact of quantization noise
is more pronounced.
Fig. 4. Post-calibrated SNDR via Monte Carlo simulations when (a) $\alpha$=1.3, (b)
$\alpha$=1.8.
We also explored how many ADC outputs are needed to reliably attain digital weights,
as this is closely related to the physical time to complete the calibration. Fig. 5 shows the simulated SNDR for an ADC output while increasing the number of ADC outputs
that are used in digital weight estimation. The graph indicates that only 70 ADC outputs
are sufficient to reach stable performance. This is in contrast to other digital weight
estimation algorithm[3-5], where up to over one thousand data points are used for comparable ADC total resolution.
Such a distinctive advantage results from that our method leverages the efficiency
of batch optimization that utilizes multiple data simultaneously when solving the
least-squares minimization problem. On the contrary, updating the digital weights
recursively at every conversion as demonstrated in [3-5][3-5] (this is also called online learning) is known to be less efficient and tends to
converge slowly.
Fig. 5. Post-calibrated SNDR versus the number of ADC output samples used in the calibration.
III. IMPLEMENTATION AND MEASUREMENT
As a test vehicle of presented calibration method, we designed a SAR ADC in 65-nm
CMOS process using a differential binary-scaled CDAC with single attenuation capacitor.
The overall ADC architecture is displayed in Fig. 6. The CDAC is designed for an effective resolution of 11-bit with extra 3-bit redundancy
by using oversized bridge capacitor. The unit capacitor size is $C_{u}$ = 22$fF$,
which is the smallest available capacitor in the foundryprovided design kit. We used
$C_{a}$=$2C_{a,ideal}$ and this value was chosen based on extracted-simulations. The
asynchronous SAR logic controls the DAC switching based on monotonic switching similar
to the method presented in [15][15]. The calibration engine consists of a 4-bit counter with reset, a weight multiplexer,
and an accumulator. The 4-bit counter generates the multiplexer selection signal by
counting up the asynchronous clock pulse, and is reset by sampling clock. The multiplexer
output sequentially provides the digital weights for each bit to the adder such that
the calibration engine can be designed using a single accumulator, which leads to
compact hardware implementation. A 16-bit width is used for all digital weights such
that the accuracy of digital weight does not limit the overall performance. The digital
calibration engine is synthesized using standard- cell library and the operation of
the calibration engine has been fully verified in transistor-level simulation, but
only the analog core is implemented on-chip. Fig. 7 shows the chip photograph along with the layout of the synthesized digital calibration
engine. The ADC analog core occupies total active area of 0.08mm2 while the synthesized digital calibration engine occupies only 0.0025 mm2, which is only 3% of the analog core. The ADC has been tested using 5 MHz of sampling
frequency under 0.7 V supply voltage and 0.6 V reference voltage. The analog core
consumes 63.75 μW of power, while the simulated digital power is 9.03 μW. The optimal
digital weights are found by first injecting sinusoid with known frequency and then
running the optimization algorithm in MATLAB. Fig. 8 shows a representative INL plot for 100 kHz input sinusoid. The INL ranging from
-8 LSB to 6.7 LSB before the calibration results from oversized bridge capacitor in
CDAC. On the other hand, the post-calibrated INL in the bottom shows that the INL
reduces to -0.68 LSB ~ +0.54 LSB after the calibration. From IEEE ENOB timedomain
best fit, peak SNDR is 62.26dB after calibration.
Fig. 6. The architecture of the prototype SAR ADC using split CDAC.
Fig. 7. The layout image on top of the die photograph.
Fig. 8. The measured residual error of ADC output with and without the calibration.
Fig. 9 also shows the FFT result of near-Nyquist input with and without calibration. Since
the measured SFDR is much higher than SNDR, the performance is primarily limited by
the thermal noise after the calibration. Lastly, we performed two sets of measurement
when 1) optimal digital weights are individually found at all input frequencies and
2) a single set of digital weight is used for all input frequency for the calibration.
This is to verify that the optimal digital bit weight is not sensitive to the input
signal frequency. Fig. 10 displays the measured SNDR versus input signal frequencies for two experiment setups.
Evidently, two lines are almost indistinguishable, implying that the error due to
the nonlinearity of the CDAC does not depend on the signal frequency. The SNDR drop
with increasing signal frequency is due to the frequency-dependent nonlinearity in
the sampling switch, which is not corrected by this calibration. Table 1 summarizes the comparison between this work and other state-of-the-art designs. The
presented calibration method, while achieving comparable power efficiency and peak
SNDR uses significantly fewer data samples (≈70 samples in this work) to obtain the
optimal digital weights required to perform digital-domain calibration when compared
to other works that use from 1000 to 1 million data samples for the calibration[3-5,10]. We believe that this characteristic can be leveraged for enhancing the efficiency
of entire ADC calibration procedure. Additionally, since our method simultaneously
finds optimal weights for all digital bits, it overcomes the limitations of adjusting
just single digital weight associated with one attenuation capacitor[3-5].
Fig. 9. Measured FFT plot with 5MHz sample rate for 2.2MHz input sinewave.
Fig. 10. SNDR versus input signal frequency for a fixed (star) and individually optimized
(circle) digital weights.
Table 1. Performance summary and comparison table
|
|
This work
|
[5][5]
|
[4][4]
|
[3][3]
|
[10][10]
|
[16][16]
|
[17][17]
|
|
Process [$nm$]
|
65
|
90
|
65
|
130
|
28
|
40
|
180
|
|
ADC Architecture
|
SAR(Split)
|
SAR(Split)
|
SAR(Split)
|
SAR(Split)
|
SAR(binary)
|
SAR(binary)
|
SAR(binary)
|
|
Supply Voltage $[V$]
|
0.7
|
1.2
|
1.2
|
0.5
|
0.81
|
0.5
|
0.6
|
|
Sample Rate [$MS/s$]
|
5
|
120
|
50
|
0.01
|
3.5
|
1.1
|
0.2
|
|
Total Power [$\mu W$]
|
72.78
|
5500
|
2090
|
0.73
|
70.5
|
1.2
|
2.4
|
|
SNDR (Peak) [$dB$]
|
62.26
|
63.7
|
67.4
|
61.8
|
68.1
|
N/A
|
58
|
|
SNDR (Nyquist) [$dB$]
|
53.53
|
60.2
|
65
|
61.6
|
N/A
|
46.8
|
50
|
|
Number of Samples for Cal.
|
70
|
1280
|
1 Million
|
N/A
|
16384
|
N/A
|
N/A
|
|
Area [$m m^{2}$]
|
0.08
|
0.042
|
0.083
|
0.582
|
0.016
|
0.112
|
0.87
|
|
FoMNyquist [$f J/conv.step$]
|
37.5
|
54.9
|
21.9
|
74.8
|
9.8
|
6.3
|
15.51 (at 10 kHz)
|
|
Digital Cal. Power [$\mu W$]
|
9.03
|
2300
|
N/A
|
0.16
|
N/A
|
N/A
|
N/A
|
FoM = Power/(2ENOB· Sample rate). No calibration is used in [16][16] and [17][17]
IV. CONCLUSION
This paper presented an efficient digital-domain calibration method that can be applied
to the calibration of SAR ADC using a bridge capacitor in CDAC The method, based on
least-squares optimization, simultaneously finds optimal digital weights for all digital
bits in ADC raw output such a way that the calibrated ADC output achieves highest
possible linearity. Both the behavioral simulation and measured result from the prototype
ADC design prove the viability of the presented calibration method, which yields optimal
digital weights that are insensitive to ADC input signal frequency in time-efficient
manner. We believe that the presented fore- ground calibration method as well as the
detailed circuit architecture of the compact digital calibration engine can be useful
resource for designing power-efficient high-resolution SAR ADC designs in nanometer
technologies.
ACKNOWLEDGMENTS
This work was supported by the faculty research fund of Konkuk University 2017. The
authors would like to thank IDEC for chip fabrication and CAD support
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Author
received the B. S. degree in Electrical Engineering from Konkuk University, Seoul,
Korea, in 2015.
He is currently working toward the ph. D degree at Konkuk University, Seoul, Korea.
His research interests include lowpower high speed Nyquist rate ADC.
received the JINTAE KIM received the B.S. degree in Electrical Engineering from Seoul
National University, Seoul, Korea, in 1997, and the M.S. and Ph.D. degrees in Electrical
Engineering from University of California, Los Angeles, CA, in 2004 and 2008, respectively.
He held various industry positions at Barcelona Design, Agilent Technologies (Now
Keysight Technologies), SiTime Corporation, and Invensense, where he worked as a key
technical contributor for various mixed-signal IC products.
He joined Konkuk University, Seoul, Korea in 2012 and is currently an Associate Professor
in Electrical and electronics Engineering Department.
His current research area is low power mixed-signal IC designs for communication and
sensor applications.
Dr. Kim currently serves on the Technical Program Committee of the IEEE Asian Solid-State
Circuit Conference (ASSCC).