I. INTRODUCTION

Wireless monitoring (i.e., a biomedical implant) is critical to implement health care systems including non-contact monitoring, bio-signal acquisition, and quick diagnosis. Although these devices have many benefits, there are still plenty of chip design challenges, especially in minimizing the power consumption and silicon area.

Among all the building blocks inside the chips, the PA is one of the most critical blocks since it dissipates large current to achieve higher power amplification. Unlike conventional PAs which operate with large-capacity batteries and mainly focus on linearity enhancement, low power PAs must focus on improving efficiency to prolong battery life.

To improve a PA performance, a current-combing topology ^[1] was utilized to simplify matching networks and optimize the PA output impedance to the antenna easily. However, high supply voltage and off-chip components degrades the power efficiency and small form-factor. An edge-combining PA ^[2] was reported to increase power efficiency by using near-threshold supply (i.e., 0.2 V) and a digitally NOR-based phase multiplexer array. However, off-chip bulky components such as capacitors and inductors are still required to maintain the required PA performance.

A class C voltage-shaping PA ^[3] was reported to achieve high efficiency without harmonic tuning by using a pulse shaping technique. However, different input power make the input capacitance varies among cut-off, subthreshold, and saturation region and thus degrades the power amplifier efficiency.

Fig. 1. Proposed PA with reconfigurable high-gain (HG) and driver-bypass (DB) modes (a) block diagram, (b) schematic.

These PA ^[1-3] lacks the flexibility of input power tuning range of PA stages. For example, the output power range of a VCO-PA topology and the a VCO, mixer, and PA architecture has huge difference for their input power range, leading to degrade the PA efficiency. To overcome the aforementioned problems, a fully integrated CMOS PA with reconfigurable driving modes is proposed to provide adaptive biasing capabilities for balanced input power range and improve PA efficiency concurrently.

The proposed PA is described in Section II. Section III provides the implementation and the measurement. A conclusion is provided in Section IV.

II. ARCHITECTURE

The schematic of proposed selectable PA using adaptive biasing technique is shown in Fig. 1(a). The circuit is comprised of three building blocks, an adjustable variable amplifier, a low loss 2:1 switch, and an efficient power stage.

For biasing method, the adaptive biasing control technique has been widely used in high output power PA design for linearity and DE enhancement ^[4-6] as well as temperature compensation ^[7]. Since the transistors are turning on and off frequently in class C operation, the input capacitance variance leads to the nonlinearity effect (AM-PM distortion) and causes the DE degradation. In the proposed work, the compact adaptive biasing circuit, shown in red in Fig. 1(b), is employed to compensate the input capacitance of M2 and M9. Hence, the DE is increased. Fig. 2 shows the comparison of the proposed PA with conventional resistor biasing and adaptive biasing. The DE increases approximately 7% at the possible operating region, from -6 dBm to -2 dBm. Moreover, the active biasing circuits are formed only with resistors and a transistor. Therefore, little silicon area is needed for employing this technique.

Fig. 2. Simulated DE comparison between fixed and adaptive biasing.

In Fig. 1, M4-M7 form the low loss switching stage. Fig. 3 shows the operating mechanism for a low loss switch that has been proposed in ^[8]. If the v_control1 is low and v_control2 is high, M4 and M6 turn on and M5 and M7 turn off. The signal (shown in blue) flows through from M6 to C6 and then to the output as shown in Fig. 3(a). On the contrary, the signal (shown in red) flows through from M4 to ground and does not appear at the output end which is shown in Fig. 3(b).

In addition, compared with conventional pass transistor logic (PTL) that only consists of one transistor, the voltage- controlled switch is composed of other two transistors (M4 and M7), which improve the port-to-port (P2P) isolation while maintaining negligible loss. Fig. 4 shows the simulated result of signal loss and P2P isolation of the proposed switch and the PTL. As shown in Fig. 4(a), the loss difference compared with the traditional PTL is only 0.24 dB at 2.4 GHz. Fig. 4(b) shows the simulated result of the P2P isolation. As it can be seen in this figure, the proposed switch improves more than 13 dB isolation ranging from DC to 5 GHz.

Fig. 3. Two modes of control voltage switching mechanism (a) DB mode; V_control1=low, V_control2=high, (b) HG mode; V_control1=high, V_control2=low.

In the proposed deign, the amplifier can operate in two modes depending on the amplitude of the signal from the previous stage. The first mode is DB mode. As shown in Fig. 1(b), if the V_control1 is low and V_control2 is high, the signal passes through C2, M6, and C6 to the power stage. The power stage is designed by using the load pull system to find out the highest DE impedance. After finding the optimum load, L2, L3, C10, C11, and C12 are employed to transform the impedance to the desired matching point. If the signal from previous stages is small, further amplification (HG mode) is required. By changing the gate bias of v_control1 and v_control2, the signal goes through M5 to the power stage. In addition, the current of the driver stage is controlled by the tail current source M1. By tuning the gate bias of M1, the drain-source resistance (Rds) is altered and thus the gain is changed. Moreover, C3 is included to compensate for the loss that caused by the Rds degeneration effect. The proposed driver stage offers a wide power gain from 3 dB to 9.6 dB while adjusting the Vbias from 0.4 V to 0.55 V.

Fig. 4. Simulated results of (a) signal loss, (b) P2P isolation.

The overall efficiency can be obtained as Eq. (1):

where $\mathrm{P}_{\mathrm{out}}$, $\mathrm{P}_{\mathrm{DC},\,\,\text{driver}\,\,\text{stage}}$, and $\mathrm{P}_{\mathrm{DC},\,\,\text{power}\,\,\text{stage}}$ represent the output power, DC power consumption of the driver stage, and DC power consumption of the power stage, respectively. In the DB mode, the $\mathrm{P}_{\mathrm{DC},\,\,\text{driver}\,\,\text{stage}}$ is set to be zero to minimized the overall power consumption to maximize the DE.

III. EXPERIMENT RESULTS

The proposed PA was fabricated in a 0.13 ${\mathrm{\mu}}$m CMOS technology. The area of the PA is 1${\times}$0.65 mm$^{2}$ including the measurement pads, as shown in Fig. 5(a). The dc power consumption of the PA is 2.85 mW and 3.86 mW for the DB mode and HG mode, respectively. Fig. 5(b) shows the demonstration setup for the PA measurement. On wafer testing is performed by using Cascode probe station with GSG and PPP probes, Agilent E5071C network analyzer for the continuous wave generation, the Anritsu MA2474D power sensor and Anritsu ML2437A power meter for the PA power measurement.

Fig. 5. (a) Chip micrograph, (b) Measurement setup.

Fig. 6 and 7 shows the result of Pout and DE for the proposed PA. The PA achieves the Pout of 0 dBm with the DE of 35.1% under 0.7 V supply in the DB mode. To provide additional amplification, with varying the vbias, the PA can provide up to 9.6 dB power gain, Pout of 0 dBm while having a DE of 26% under 0.7 V supply, as shown in Fig. 6-8. Noted, the DE is limited by the on-chip passive component with low quality factor, the DE can be improved if the matching network is implement off-chip but with the expense of additional PCB and wire-bonding. In addition, for the $vbias$ is less than 0.4 V, the tail current source goes to the triode region which might induce more nonlinear effect. As the result, the tuning range of $vbias$ lies from 0.4 V to 0.55 V for reliable operation

Fig. 6. Measured output power in DB and HG mode.

Fig. 7. Measured output DE performance in DB and HG mode.

Fig. 8. Measured gain in DB and HG mode.

Table 1 shows a performance comparison with key parameters containing the summary of recent state-of-art works and the proposed PA. Utilizing both adaptive biasing technique and voltage-controlled switch implementation, the proposed design has low power consumption along with tunable high gain and fully integrated passive components compared to the previous state-of-art works that operate in similar frequency band.

IV. CONCLUSIONS

A silicon-proved fully integrated tunable PA with adaptive biasing techniques has been successfully implemented. With the adaptive biasing, the DE is improved by 8%. The voltage controlled switch enables dual mode operation to provide either efficient signal transfer or high gain amplification depending on the signal amplitude. The PA has been fabricated in a 130 nm CMOS technology and achieves a DE of 35.1% and 26%, a gain of 1 dB and 9.6 dB under 0 dBm output power for DB mode and HG mode, respectively.