I. INTRODUCTION

To develop a power device that operates at a high voltage and high current, a material with a wide-band-gap must be used, instead of Si. 4H-SiC is a wide-band-gap material and has a high critical electric field. Thus, the 4H-SiC device has a high breakdown voltage and is advantageous for high-voltage and high-current operation ⁽¹⁾. Currently, a typical power device that uses 4H-SiC is the trench metal oxide semiconductor field-effect transistor (UMOSFET). However, trench MOSFETs suffer from electric field crowding at the gate-trench edge, which creates a high electric field on the gate oxide making the device unreliable ⁽²⁾. To address this problem, a structure in which a “shield” is formed through p-type doping under a gate trench is most commonly used [Fig. 1 (a)]. In the case of highly doped p-type shields, the depletion region barely expands, thus preventing the electric field from being applied to the gate oxide. Recently, a double-trench MOSFET (DT-UMOSFET) structure has been used to mitigate electric field crowding [Fig. 1 (b)] ⁽³⁾. This structure distributes the electric field concentrated on the gate-trench by the deep p-type doping of the source region. Accordingly, the breakdown voltage of the device can be increased and on-resistance can be decreased. In addition, the electric field cannot be concentrated in one place but evenly distributed in the epi-region, thereby increasing the breakdown voltage of the device.

The device characteristics were analyzed by two-dimensional TCAD simulation. The mobility models included doping dependent, high field velocity saturation and mobility degradation ⁽⁴⁾. Model for the anisotropic and incomplete ionization effects was also included ^(5),(6). And temperature-dependent Shockley-Read-Hall and Auger recombination were considered in the simulation. This is the Lombardi model and the model parameter is shown in Table 1.

Fig. 1. Structure of (a) Conventional UMOSFET (CUMOSFET), (b) Double Trench MOSFET (DT-UMOSFET), (c) Source Trench UMOSFET (ST-UMOSFET).

Table 1. Lombardi model parameters for 4H-SiC

II. PROPOSED STRUCTURE

An important principle that we trench in the source region is to increase the breakdown voltage by dispersing the electric field applied to the gate oxide to the source trench region. The larger the electric field is distributed in the source trench region, the less electric field remains in the gate oxide region. In the DT-UMOSFET a p-+ doping region is added to the source-trench to dissipate the electric field applied to the trench gate. However, the critical field of 4H-SiC (2–3MV/cm) is lower than that of the thermally grown oxide (6.8–9MV/cm) ^(7),(8). If a thermally grown oxide is used in the source-trench, the device can withstand higher electric fields, resulting in higher breakdown voltages. For devices with the same breakdown voltage, it is possible to vary the specification of the epi-layer to achieve a lower on-resistance. Therefore, we propose a UMOSFET with a source-trench oxide structure (ST-UMOSFET). ST-UMOSFET has a structure in which an oxide layer is formed on a source-trench to withstand a higher electric field [Fig. 1 (c)]. When the device breaks down, a higher electric field acts on the source-trench oxide than on the gate-trench. Thus, even if a higher drain voltage is applied, the breakdown voltage of the device can be maximized because it can withstand a higher electric field at the source-trench oxide. In addition, when the same drain voltage is applied, the electric field applied to the gate oxide can be reduced because the electric field distributed by the source-trench oxide is larger than that of the gate-trench. If a device with the same breakdown voltage is fabricated, the doping concentration in the epi-layer can be increased as the breakdown voltage increases. Accordingly, the doping concentration of the epi-layer is increased and the on-resistance of the device can be reduced.

III. SIMULATION RESULT AND DISCUSSION

1. Breakdown Voltage Characteristics

To investigate the effect of the source-trench and oxide on the device structure, a simulation was performed on the device in the following order: conventional UMOSFET (C-UMOSFET), DT-UMOSFET, and ST-UMOSFET. The thickness and doping concentration of the epi region were combined to measure the breakdown voltage and electric field applied to the gate oxide. The Sentaurus T-CAD tool was used to analyze the static characteristics of each device.

Table 2. Device parameters of C-UMOSFET, DT-UMOSFET, and ST-UMOSFET

Fig. 2 shows the intensity of the electric field applied to the gate oxide in each structure. A lower electric field, compared to that in the C-UMOSFET, is applied to the gate oxide in the DT-UMOSFET structure. In the ST-UMOSFET, a lower electric field, compared to that applied to the DT-UMOSFET, is applied to the gate oxide. Because of the high critical electric field in the source-trench oxide, a higher electric field is applied to the source-trench. Fig. 3 shows the electric field distribution at the gate-trench position when 800 V is applied to the drain. The ST-UMOSFET exhibits the lowest electric field distribution, which means that a significant amount of electric field is distributed toward the source-trench. Specifically, the ST-UMOSFET can have a higher breakdown voltage because the electric field applied to the epi-region is lower than those applied to the epi regions in the other structures.

Fig. 4 shows the breakdown voltage of the three structures. The breakdown voltages of C-UMOSFET, DT-UMOSFET, and ST-UMOSFET are 1693, 1935, and 1967 V, respectively. Compared to the C-UMOSFET, the DT-UMOSFET has a higher breakdown voltage because it minimizes the electric field crowding. The ST-UMOSFET has a higher breakdown voltage than the DT-UMOSFET due to the use of an oxide with a high critical electric field for the source-trench.

Fig. 2. Electric field distribution in (a) C-UMOSFET, (b) DTUMOSFET, (c) ST-UMOSFET.

Fig. 3. Electric fields in C-UMOSFET, DT-UMOSFET, and ST-UMOSFET in the vertical direction.

Fig. 4. Breakdown voltages of the C-UMOSFET, DTUMOSFET, and ST-UMOSFET.

2. On-resistance Characteristics

As seen above, since the breakdown voltage is different at the same thickness and concentration of the epi-layer, the on-resistance characteristics are compared when the breakdown voltage is the same. That is, when the breakdown voltage of each structure is designed to be 1700V, the doping concentration of the epi layer is changed as given in Table 3. The breakdown voltage for each structure is shown in Fig. 5. The output characteristics of each structure are shown in Fig. 6. The gate voltage was 6V. The calculated on-resistances of C-UMOSFET, DT-UMOSFET, and ST-UMOSFET from Fig. 6 are 34, 28, and 18 mΩ·cm$^{2}$, respectively. Because DT-UMOSFETs have higher breakdown voltages than C-UMOSFETs, the doping concentration of the epi-layer can be higher for devices with the same breakdown voltage. Likewise, ST-UMOSFET can also facilitate an increase in doping concentration of the epi-layer compared to DT-UMOSFET.

Table 3. Epi-layer doping concentration of C-UMOSFET, DTUMOSFET, and ST-UMOSFET

Fig. 5. Breakdown voltages of the C-UMOSFET, DTUMOSFET, and ST-UMOSFET (epi-layer specification in Table 3).

Fig. 6. Output characteristics of the C-UMOSFET, DTUMOSFET, and ST-UMOSFET.

Fig. 7. Change in the breakdown voltage of the ST-UMOSFET according to source trench depth variation.

IV. FABRICATION

Fig. 8. shows the fabrication procedure of the proposed structure, the feasibility of which is demonstrated in this study. P-body and n+ source are formed using double diffusion [Fig. 8. (a)]. Etch the gate trench and ion implant the p+ shield [Fig. 8. (b)]. Fill the gate trench with SiO$_{2}$ [Fig. 8. (c)] and pattern it using photoresist [Fig. 8. (d), (e)]. Etch the source trench using patterned SiO$_{2}$ as a mask [Fig. 8. (f)]. Remove SiO$_{2}$ filling the gate trench [Fig. 8. (g)] and perform source oxidation [Fig. 8. (h)]. In this case, SiO$_{2}$ of the same thickness is grown as sacrificial oxide in the gate trench. Deposit and pattern Nitride film [Fig. 8. (i)]. Grow gate oxide and strip nitride film [Fig. 8. (j)]. Deposit poly-Si in the source and gate regions [Fig. 8. (k)]. The final structure is completed through Poly-Si etch back process [Fig. 8. (l)].

Fig. 8. Fabrication sequence of ST-UMOSFET.

V. CONCLUSION

We have proposed an ST-UMOSFET structure with an oxide layer on the source-trench. Because of the high critical electric field of the thermally grown oxide, the electric field of the gate oxide could be more distributed. The electric field was not concentrated in one place but was dispersed; thus, the breakdown voltage of the device increased. Consequently, the ST-UMOSFET has a breakdown voltage of 274 V that is higher than that of the C-UMOSFET. In addition, the electric field applied to the gate oxide was relaxed from 1.9 MV/cm to 0.7 MV/cm. When a device with the same breakdown voltage is designed, the doping concentration of the epilayer can be set high and therefore the on-resistance can be reduced. Because the ST-UMOSFET has a higher breakdown voltage than the C-UMOSFET, the doping concentration of the epi-layer can be set high. Accordingly, the on-resistance of the ST-UMOSFET is reduced by 47% compared to the C-UMOSFET. The STUMOSFET has higher reliability and has characteristics that are favorable for high-voltage, high-current operation