1. Pre-amplifier

Since the ocean measurement environment requires the use of a low noise receiver due to the presence of various noise sources, one of the most important issues is increasing the signal-to-noise ratio (SNR) in the high-resolution receiver. In order to increase the SNR, it is necessary to first lower the noise level of the input signal to the ADC. In the receiver proposed in this paper, the pre-amplifier is designed to lower the noise power for high SNR at the output of the ADC. In general, the IR noise of the pre-amplifier dominantly determines the noise performance of the whole receiver. Therefore, in order to design a receiver with low noise, it is important to minimize the IR noise of the pre-amplifier. In addition, the pre-amplifier suppresses the noise from VGA1 and BPF by providing a gain of 20 dB. A schematic diagram of the pre-amplifier is shown in Fig. 5.

Fig. 5. Schematic of pre-amplifier.

Since the input DC voltage level of the application is not determined by the external sensor, we design the pre-amplifier to shift the DC level to 1.2 V in order to satisfy the bias condition of VGA1. The size of VGA input MOSFET is optimized in order to minimize the input referred noise. Using this pre-amplifier, the IR noise of the proposed receiver is simulated to be 29.6 nV / √Hz at 50 kHz.

Fig. 6. Schematic of OP-Amp in the Pre-Amplifier.

Fig. 6 shows the Two-Stage OP-Amp with PMOS inputs used in the pre-amplifier. Miller compensation with R and C is applied so as to guarantee the Phase Margin (PM) of 60 °. The noise contributions of all of the devices in the OP-Amp are analyzed, with the results shown in Fig. 7. As shown in Fig. 7, the IR noise is lowered by optimizing the MOSFET size and the bias current. Prior to optimization, the flicker noises of the input MOSFETs are the dominant factor. Thus, we reduce their noise to almost 1/10 of their pre-optimization value. Fig. 8 presents the IR noise simulation result of the pre-amplifier, showing the noise of 28 nV/√Hz at 50 kHz.

Fig. 7. IR noise comparison before optimization and after optimization at 0.18 μm CMOS process.

Fig. 8. IR noise simulation result of pre-amplifier.

2. Variable Gain Amplifier

In order to ensure the high resolution of the SD ADC, precise gain control is needed. The proposed receiver controls the gain with 1-dB step. As shown in Fig. 2, the input signal goes through the VGA1, BPF, and VGA2 sequentially. The maximum gains of both VGA1 and VGA2 are 40 dB. Fig. 9 shows a schematic diagram of VGA1; VGA2 uses the exact same structure as VGA1.

Furthermore, they are designed to be adjustable using a resistive feedback structure by 1-dB step control depending on the input signal level. As the signal amplitude grows, a lower gain is provided in order to satisfy the input voltage range of the SD ADC. The AC simulation result of VGA1 is shown in Fig. 10. The total gain ranges from 0 dB to 40 dB and it provides a variable gain step of 1-dB.

Fig. 9. Schematic of VGA1.

Fig. 10. AC simulation result of VGA1.

3. Band Pass Filter

An Active-RC Band-Pass Filter (BPF) is implemented in the proposed receiver in order to cancel the dc offset and suppress noise at high frequency. A schematic diagram of the BPF is shown in Fig. 11. The BPF is designed as a fourth order, Chebyshev type. In terms of noise performance, VGA1 is positioned immediately after the pre-amplifier because the noise characteristic of BPF is worse than those of the VGA1 and VGA2. Thus, the noise from BPF can be attenuated by the gain of the pre-amplifier and VGA1.

Fig. 11. Schematic of Band-Pass Filter (BPF).

4. Sigma-delta ADC

Fig. 12 shows the proposed simplified SD ADC designed in this work. The SD ADC consists of an SDM and a digital filter. In this application, we designed it to have a high resolution for the ocean measurement environment. In order to reduce the noise, the SDM is designed to push the noise to a higher frequency so that it can be filtered by the following digital filter. A decimation filter is designed to control the decimation factor so as to lower the current consumption.

Fig. 13 shows a block diagram of the SDM. The second order discrete type SDM with a Cascaded Integrator Feed-Back (CIFB) structure is implemented.

Fig. 12. Simplified block diagram of the proposed SD ADC.

Fig. 13. Block diagram of the Sigma-Delta Modulator (SDM).

Two integrators and a 1-bit Quantizer are used. A schematic diagram of the SDM is shown in Fig. 14. The sampling operation is performed in the sampling capacitors as shown in Fig. 14. The differential signals ($V_{REFT}$ and $V_{REFB}$) originate from the analog circuits, including the pre-amplifier, VGA, and BPF. The input differential range of SDM is 2 $V_{pp}$ and the common mode level is 1.2 V. In the first integrator, the coefficient value is determined by the ratio of the sampling capacitor ($C_{I}$/4) and integration capacitor ($C_{I}$).

Fig. 14. Schematic of the designed Sigma-Delta Modulator (SDM).

Fig. 15. Schematic of OP-Amp in the proposed SDM.

Fig. 15 shows a schematic diagram of the OP-Amp used in the SDM shown in Fig. 14; it has a gain-boosted Folded-Cascode structure. In order to reduce the flicker noise at low frequency, the chopping scheme is applied. The OP-Amp uses the Chopper PMOS, Chopper NMOS, and Chopper_IN along with their control switches. The chopper pushes the noise in the signal band to a higher frequency. The chopper circuits basically operate based on the clock, which is generated by the CLK Generator, as shown in Fig. 15. In addition, the common mode feedback (CMFB) circuit is designed to keep the output common mode voltage level constant. Since it is in the high gain amplifier, the use of a circuit that maintains the output bias voltage is essential. In order to use a high sampling frequency, the CMFB clock should be separated from the sampling clock. If the CMFB clock is the same as the sampling clock, the gain of the OP-Amp used in the SDM will be reduced, and consequently, the resolution of SD ADC will also be degraded. In this paper, we split the CMFB clock from the sampling clock.

Fig. 16. Structure of the non-overlapped two-phase clock generator.

Fig. 16 shows a schematic diagram of the clock generator of the SDM. The circuit generates clock signals $Q_{1}$, $Q_{1D}$, $Q_{2}$, and $Q_{2D}$. In addition, the inverted signals of $Q_{1B}$, $Q_{1DB}$, $Q_{2B}$, and $Q_{2DB}$ from $Q_{1}$, $Q_{1D}$, $Q_{2}$, and $Q_{2D}$, respectively, are also generated by the clock generator circuit.

Fig. 17. Clock signals generated by the CLK Generator.

Fig. 18. Structure of the comparator.

Fig. 17 shows the clock signal waveforms generated by the clock generator circuit. Since $Q_{1B}$, $Q_{1DB}$, $Q_{2B}$, and $Q_{2DB}$ are inverted forms of the $Q_{1}$, $Q_{1D}$, $Q_{2}$, and $Q_{2D}$ signals, respectively, the $Q_{1}$ and $Q_{2}$ signals are non-overlapped clocks, as are the $Q_{1D}$ and $Q_{2D}$ signals.

Fig. 18 shows the structure of the proposed comparator. Since the associated power consumption is less than that of the static type, a dynamic type of comparator is designed.

The differential output of the second integrator is connected to the INP and INN inputs of the comparator. The outputs of the comparator (SDM_OUT and SDM_OUTB) are determined by latches. The $Q_{1}$ and $Q_{2}$ clock signals control the comparator clocking, and the P1 and N1 signals control certain switches in the SDM, as shown in Fig. 14.

The proposed SD ADC mainly consists of an SDM and a digital filter. The digital filter cuts the noise on the high frequency band. The main function of the SDM is to push the noise to a higher frequency than the input signal frequency. In addition, the order of the SDM determines the slope of the output noise shaping. The use of a higher order SDM leads to sharper output noise shaping on the frequency domain. In order to apply a digital filter to the high order SDM, the digital filter should have high power and a large area with a cascaded structure. In the conventional design, the decimation factor of the digital filter is dependent on the OSR of the SDM. In this paper, a digital filter with a controllable decimation factor and controller is presented.

Fig. 19. Proposed block diagram of the decimation filter.

The SDM in this paper has a second order configuration, as shown in Fig. 13. For the small area, a sinc3 type filter is adopted for the proposed receiver. The block diagram of the proposed decimation filter is shown in Fig. 19 to include the Integrators and Comb filters with a cascaded structure. The controller is used to control the decimation factor. Using the CONTROLLER block, the register width and proper clocking within the filter stages can be selected. The Integrator clock is the same as the sampling clock (Fs) of the SDM, whereas the Comb can be operated with the sampling clock divided by the decimation ratio (Fs/D). This process helps the decimation filter reduce the power dissipation at the Comb stage of the CIC filter. This clock is controlled by the CONTROLLER block according to the requirements of the decimation ratio. The register size can be varied through the CONTROLLER by changing the decimation ratio. This is because integration and differentiation (Comb) require different register sizes with different decimation ratios; the register sizes are proportional to the decimation ratio as expressed by the following Eq. (1).

In this Eq. (1), L is the number of stages in the CIC filter. In addition, D is the decimation factor with variable features, M is the number of delays, and Win is the input word length. Inside the integrator and comb filter, the register size is controlled for the specific decimation ratio. The output of the filter has the 14 Most Significant Bits (MSB) selected from the single wide register (main register).

Fig. 20. Proposed controller for configurable CIC filter.

Fig. 20 shows the CONTROLLER used in the decimation filter, which includes the Clock Controller and the Register Controller. The Clock Controller provides the clocks needed in the Comb filter, Integrator, and CIC filter. Eq. (1) shows how the register size is calculated as well as the maximum size for D=2048. This will be the main register used by all of the filters. The controller will select MSB 14-bits from this register based on the decimation factor and discard the remaining bits.

The controller operates by sampling the clock sample with that used in the SDM. The necessary clocks for the integrator, comb, and other control blocks are generated based on this sampling clock. D_CNTRL (4 bits) is used to select from the various decimation factors that are available (32, 64, ..., 2048). The register controller block selects 14 MSBs from the main register and assigns them to the output by dropping the LSB.

5. P2S-S2P Interface

The proposed receiver implements the serial interface circuit inside the IC. For pin-constrained applications, a P2S interface is necessary to transmit the data ⁽¹⁰⁾.

Fig. 21. P2S and S2P block diagram.

Fig. 21 shows a block diagram of the P2S-S2P used in the proposed receiver, where SYNC is the synchronization signal, DIN means parallel data input, and SDO is serial data output. The P2S interface is designed inside the IC and S2P is in the FPGA board. The ADC outputs the parallel data, which then goes to the P2S interface, whose output is serial form data. This P2S-S2P interface has two synchronization modes: high throughput mode (HTM) and highly synchronized mode (HSM).

In HTM, at first, SYNC is pulled down and the MODE signal is high. Then, P2S receives data from DIN, and at the active edge of clock SCK, transmits it to SDO. SDO is then transmitted in serial from MSB to LSB. In this mode, no overhead bits or extra clock cycles exist. At the time that the communication between the P2S and S2P interfaces begins, P2S and S2P are synchronized once at the negative edge of SYNC. First, MODE is pulled down, and the mode HSM, in which P2S and S2P synchronize, is enabled after all serial data is sent and received. Only when RD is high, P2S takes the sample and transmits it to P2S. This mode is selected due to the features of the proposed receiver, which does not require continuous data. In order to achieve high performance P2S interface operation, $f_{sck}$ (the serial clock frequency) is necessary. This is given in Eq. (2).

In Eq. (2), N is the resolution and FADC is the sampling frequency of ADC. The P2S and S2P interfaces are in a synchronous finite state machine (FSM) model-based design. Fig. 22 shows the FSM flow chart for P2S and S2P. The timing diagram of each piece of data is presented in Fig. 23. In this paper, the P2S circuit is only enabled when EN from the control logic is pulled high. For P2S, the positive or negative active edges can be selected by the clock edge select signal (CES). In the POWER_UP stage, the P2S controller moves to ENABLE. Then, the controller goes to the SYNC_DET state and holds on to the SYNC negative edge. When SYNC is released from S2P, the P2S controller jumps to the next stage, LOAD_STX. In the LOAD_STX state, the parallel data DIN is loaded from the internal register transmitting the MSB to SDO. Then, in the SHIFT_STX state, if SYNC is kept low, the internal register value is shifted one bit to the left, and the MSB of the register is transferred to the SDO pin, remaining for N-1 SCK clock cycles. If HTM is enabled, the controller moves state to LOAD_STX in order to take an SD ADC sample. The controller then either returns to the LOAD_STX state so as to receive the next ADC sample or jumps back to SYNC_DET for resynchronization in the case of HSM. The FSM for the S2P controller is shown in Fig. 15(b). The data remain in the POWER_UP state after reset for one clock cycle, then go to MODE_SEL state, and the MODE signal from control logic selects the mode of either HTM or HSM. When the MODE is asserted, HSM is enabled and the controller changes the direction toward the HTM_MODE state.

Fig. 22. Serial interface FSM diagram.

Fig. 23. Serial interface timing diagram.

In this state, SYNC is pulled low so as to allow for synchronization between S2P and P2S. In addition, S2P enables the SCLK clock and begins receiving serial data at SDI from S2P. The bits are shifted in serial inside the internal register. There is a counter for checking the number of bits received from P2S. If N bits are received, N-bit DOUT loads the register bits. Additionally, in order to announce to control logic that the data have been received, RD is changed to pulled high for one clock.

If MODE is deasserted to select HSM during HTM, the controller goes to the RF_DETECT state after processing the data. When HSM is enabled, the controller moves to the SHIFT_DATA state after waiting for the assertion of RD on the RD_DETECT state. Then, SYNC is pulled down and shifts serial data to an internal register on all rising edges of CLK. This is the process of receiving N-1 bits. Then., when SYNC is pulled up in the SHIFT_EXTRA state, another shift is performed. In the LOAD_DATA state, N-bits on the internal register go to DOUT. When the state changes to the RD_DETECT state, there is an announcement indicating that the data are ready. In the RD_DETECT state, the controller senses the RD signal after checking the mode switch condition. After synchronization, with continuous high RD, the HSM-CR of the S2P remains in the same state so as to enable RD in HSMSR sub-mode or launch to receive the serial stream.