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Active feedback, bandpass filtering, blocker rejection, channel-selection, FEM-less, low noise amplifier, gain-boosted, N-path filter, notch, TX leakage rejection

I. INTRODUCTION

Currently, a complicated and bulky RF front-end module (FEM) is used to support multiple cellular standards with multiple frequency bands, as shown in Fig. 1(a). To support 5G sub-6GHz standard as well as legacy, the number of sub-blocks in the FEM, such as the switches, surface acoustic wave (SAW) filters/duplexers, and power amplifiers (PAs) rapidly increases. Consequently, the FEM has become bulky, expensive, and complex. To overcome these problems, a highly integrated reconfigurable RF front-end for 3G/4G cellular applications was proposed in (1) and shown in Fig. 1(b). To implement this FEM-less transceiver, the most significant challenge was the design of the channel-selection low-noise amplifier (LNA). Because CMOS tunable duplexers that adopt an electrical balance still suffer from limited linearity and out-of-band (OB) blocker rejection ratio compared with commercial off-chip SAW duplexers (2-4), high-Q RF filtering of the channel-selection LNA is essential to support the insufficient blocker rejection of the CMOS duplexer. To optimize the overall performance, the CMOS tunable duplexer and channel-selection LNA were co-designed in (5,6).

Fig. 1. (a) Conventional 3G/4G transceiver with commercial FEM, (b) Proposed FEM-less transceiver.

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Fig. 2. Gain-boosted N-path bandpass filtering LNA (12)

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In this paper, a CMOS tunable channel-selection LNA that employs an active feedback technique and a gain-boosted N-path bandpass filter (BPF) is proposed as a key block of the FEM-less receiver for advanced cellular applications. The proposed LNA achieves broadband input power matching, low noise figure (NF), and high-Q RF bandpass filtering. The proposed topology and detailed circuit implementation of the LNA are introduced in Section II. The simulation results are discussed in Section III. Finally, Section IV concludes this paper.

II. PROPOSED CHANNEL-SELECTION LNA WITH ACTIVE FEEDBACK AND GAIN-BOOSTED N-PATH BPF

An N-path filter is the best method to design a high-Q RF filter by converting the baseband filter characteristics into RF frequencies (7-14). Generally, the OB rejection ratio of a second-order N-path filter is limited in the range 10 - 15 dB because of the on-resistances of the switches (9,10). Recently, N-path filters that overcome this limitation have been introduced in (6,11-13). A four-path BPF based on a fourth-order Gm-C BPF topology that enhanced OB rejection was also reported, but it had high power consumption and limited NF (11). A gain-boosted N-path bandpass filtering LNA was proposed in (12) and shown in Fig. 2. The four-path notch feedback LNA could provide fourth-order high-Q RF filtering because the Miller effect generates second-order RF filtering at both input and output nodes. Furthermore, the Miller effect boosts the effective feedback capacitance and reduces the on-resistance of the switches in N-path filters. Consequently, its OB rejection ratio is improved. However, the feedback resistor RF, which is used for input power matching, degrades the noise performance. A hybrid N-path BPF/band rejection filter (BRF) feedback LNA that provides two additional rejection band around the passband (13) and a tunable active BPF with adjustable transmission zero (14) were introduced as well, but they consume a lot of bias current. A channel-selection LNA with an N-path poly-phase filter was also proposed (1,15).

A channel-selection LNA topology to improve the NF performance of a gain-boosted N-path bandpass filtering LNA introduced in (12) is proposed. The simplified block diagram and schematic of the proposed LNA are shown in Fig. 3. The proposed LNA has two feedback loops. One is the four-path notch filter feedback loop for high-Q fourth-order RF filtering and the other is the active feedback loop for input power matching and NF enhancement. The active feedback reduces the adverse effect of RF on the overall LNA performances. A differential hybrid voltage follower (DHVF), instead of a conventional source follower, is employed for the active feedback loop to increase the loop gain (16). To drive four-path notch filter, 25% duty-cycle non-overlapped local oscillator (LO) signals are used. The 25% duty-cycle LO signals are implemented by logically ANDing the in-phase and quadrature signals generated by dividers (17).

The input impedance of the resistive and N-path notch filter feedback LNA shown in Fig. 2 can be approximately expressed as

(1)
$$Z_{IN,\textit{Conventional}}\cong \frac{R_{F}+R_{L}}{1+g_{m}R_{L}}\parallel \left(R_{SW}+R_{P}\right)\cong \frac{R_{F}}{g_{m}R_{L}}$$

Fig. 3. Proposed channel-selection LNA with dual feedback loop (a) Simplified block diagram, (b) Schematic.

../../Resources/ieie/JSTS.2020.20.5.423/fig3.png

where gm is the overall transconductance of the Gm-stage; RL, RF, RSW, and RP are the output resistance, feedback resistance, on-resistance of the switch, and equivalent resistance of the four-path notch filter, respectively; and gmRL is the loop gain of the feedback loop (TTLOOP,Conventional). We assume that gmRL >>1, RF >> RL, and RSW + RP >> RF at RF frequencies for intuitive and simple analysis. When the input power matching condition, i.e., ZIN is equal to source resistor RS, is satisfied, RF = TLOOP,ConventionalRS. According to (23) in (12), the noise contribution of RF is a dominant factor that determines the overall noise characteristic of the LNA because a large value of RF cannot be selected. The proposed active feedback LNA enhances the loop gain of the feedback loop. The loop gain of the proposed LNA can be expressed as (18)

(2)
$$T_{\textit{LOOP}\mathit{,}\textit{Proposed}}\cong \left(1+\beta \right)g_{m}R_{L}$$ $$\cong \left(1+\beta \right)T_{\textit{LOOP}\mathit{,}\textit{Conventional}}$$

where ${\beta}$ denotes the ratio of gmN3 to gmN5, gm = gmN1 || gmP1, RL = roN1 || roP1 || RB2, and gmi and roi are the transconductance and output impedance of the Mi transistor, respectively. The loop gain of the proposed LNA can be increased by (1 + gmN3 / gmN5) The input impedance of the proposed LNA can be approximately calculated as

(3)
$$Z_{IN,\textit{Proposed}}\cong \frac{R_{F}+1/g_{mN5}}{1+\left(1+\beta \right)g_{m}R_{L}}\cong \frac{R_{F}}{\left(1+\beta \right)g_{m}R_{L}}$$

According to (3), RF can be increased to 2TLOOP,ConventionalRS when ZIN = RS and gmN3 = gmN5 for simplicity. Therefore, the noise contribution of RF is significantly reduced, improving the overall NF performance.

The voltage gain of the proposed LNA from voltage source VS to differential output voltage VOUT can be derived as follows.

(4)
$$A_{V}\cong - \frac{2R_{F}}{R_{S}}\frac{T_{\textit{Loop}\mathit{,}\textit{Proposed}}^{\boldsymbol{*}}}{1+T_{\textit{Loop}\mathit{,}\textit{Proposed}}^{*}}$$

T*LOOP,Proposed represents the loop gain of the active feedback loop when source resistor RS is connected to the input terminal and can be expressed as

(5)
$$T_{\textit{Loop}\mathit{,}\textit{Proposed}}^{\boldsymbol{*}}\cong (1+\beta )\frac{\frac{R_{S}}{2}}{R_{F}+\frac{R_{S}}{2}+\frac{1}{g_{mN5}}}g_{m}R_{L}$$

The voltage gain of the proposed LNA is closer to $-$2RF / RS than that in (12) because T*LOOP,Proposed is approximately increased by (1 + ${\beta}$).

III. SIMULATION RESULTS

The CMOS tunable channel-selection LNA that employs the active feedback technique and gain-boosted N-path BPF is designed in a 65-nm CMOS process. The layout of the LNA is shown in Fig. 4. The active area without the bond pads is 0.8 mm$^{2}$. It draws a DC bias current of 21 mA from a supply voltage of 1.2 V. Fig. 5 shows simulated S11 versus RF frequencies. The obtained S11 from 0.1 GHz to 4 GHz is below $-$10 dB. Thus, the LNA can support all FDD bands in the 3G/4G/5G sub-6~GHz cellular standards. Fig. 6 shows the simulated voltage gain of the proposed LNA. The obtained voltage gain at the center frequency is more than 16.5 dB at the low band and 12 dB at the mid/high band. The transmitter leakage or OB blocker can be rejected by more than 15.4 and 19 dB at 40 and 80 MHz offset frequencies, respectively. Fig. 7 shows the detailed frequency response characteristic at Band 2. The 3-dB bandwidth of the proposed LNA can vary from 10 to 20~MHz by adjusting the capacitances of the four-path notch filter. The simulated NF is shown in Fig. 8. The obtained NF is approximately 2.3 dB at the low band and 3.4 dB at the mid/high band. Fig. 9 shows the simulated in-band (IB) input-referred third-order intercept point (IIP3) and OB-IIP3. The two-tone test conditions for the IB-IIP3 are f1 = fLO + 0.5 MHz, f2 = fLO + 0.6 MHz and pf1 = pf2 = ${-}$50 dBm, where fLO is the receiver LO frequency. The obtained IB-IIP3 is 8.5-10.7 dBm. The two-tone test conditions for the OB-IIP3 are f1 = fTX, f2 = 2fTX - fLO - 1MHz and pf1 = -28 dBm, pf2 = ${-}$15 dBm where fTX is the transmitter frequency. The obtained OB-IIP3 is 16.8-18.7 dBm. Table 1 lists performance summary of the proposed LNA and the comparison with previous works of RF filters and LNAs. The proposed LNA obtained the similar NF performance to that of (12). It can be considered that the proposed differential LNA enhances the NF performance because the LNA in (12) is single-ended. Compared with other previous works, it achieves low NF and high OB linearity while consuming low power and supporting all FDD bands for advanced cellular applications.

Fig. 4. Layout of the proposed LNA.

../../Resources/ieie/JSTS.2020.20.5.423/fig4.png

Fig. 5. Simulated S11.

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Fig. 6. Simulated frequency response.

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Fig. 7. Simulated frequency response at Band2.

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Fig. 8. Simulated NF.

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Fig. 9. Simulated IB-IIP3 and OB-IIP3.

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Table 1. Simulated performance summaries of the proposed LNA and comparison with previous state-of-the-art works

Parameters

Unit

MWCL2020 (1)

TMTT2014 (12)1)

RFIC2016 (13)

TMTT2016 (14)

This Work1)

Circuit type

-

Filter

LNA

LNA

Filter

LNA

Process

-

65-nm CMOS

65-nm CMOS

32-nm SOI

65-nm CMOS

65-nm CMOS

Architecture

-

N-path

N-path

N-path

N-path

N-path

Input type

-

Single-ended

Single-ended

Differential

Differential

Differential

RF filter order

-

6(BPF) + 2(BRF)

4(BPF)

4(BPF)+4(BRF)

6(BPF) + 2(BRF)

4(BPF)

Frequency

GHz

0.7 - 2.2

0.5 - 2

0.4 - 6

0.1 - 1.4

0.1 - 4

Voltage gain

dB

20.4

12.5

60

23

17

NF

dB

3.24 - 5.4

2.14 - 2.23

3.6 - 4.9

3 - 4.2

2.16 - 4.25

OB-IIP3

dBm

172)

123)

36

234)

18.72)

Power

mW

15.6

7

81 - 209

50 - 73

25.26)

Area

mm2

0.62

NR5)

0.28

2.4

0.8

1) Simulated results. 2) Two-tone test: f1 = fTX, f2 = 2fTX - fLO - 1 MHz. 3) Two-tone test: f1 = 552 MHz, f2 = 604 MHz. 4) Two-tone test: f1 = 1.045 GHz, f2 = 1.092 GHz. 5) NR: Not reported. 6) Power consumption without LO block

IV. CONCLUSION

A CMOS high-Q channel-selection LNA with dual feedback loop is proposed and designed as a key block to implement an FEM-less receiver for advanced cellular applications. The proposed LNA achieves broadband input power matching, low NF performance, and fourth-order RF filtering. It can cover all FDD bands in the 3G/4G/5G sub-6 GHz standards. Designed in a 65-nm CMOS process, the implemented LNA achieves a maximum voltage gain of 17 dB, minimum NF of 2.16~dB, and maximum OB blocker rejection ratio of 21 dB at an 80 MHz offset frequency.

ACKNOWLEDGMENTS

This work was supported in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education under Grant NRF-2018R1D1A1B07042804 and in part by the Ministry of Science and ICT, Korea, under the Information Technology Research Center Support Program supervised by the Institute for Information and Communications Technology Promotion (IITP) under Grant IITP-2020-2018-0-01433. The chip fabrication and EDA tool were supported by the IC Design Education Center (IDEC), Korea.

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Author

Donggu Lee
../../Resources/ieie/JSTS.2020.20.5.423/au1.png

Donggu Lee received the B.S. degree from the Department of Electronics Engineering, Kangwon National University, Chuncheon, Korea, in 2019.

He is currently working toward the M.S. degree in the Department of Electronics Engineering, Kangwon National University, Chuncheon, Korea.

His research interests include CMOS RF/analog integrated circuits and RF system design for wireless communications.

Kuduck Kwon
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Kuduck Kwon received the B.S. and Ph.D. degrees in Electrical Engi-neering and Computer Science from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2004 and 2009, respec-tively.

His doctoral research was on digital TV tuners and dedicated short-range communi-cation (DSRC) systems.

From 2009 to 2010, he was a Post-Doctoral Researcher with KAIST, where he studied a surface acoustic wave (SAW)-less receiver and developed RF transceivers for DSRC applications.

From 2010 to 2014, he was a Senior Engineer with Samsung Electronics Co. Ltd., Suwon, Korea, where he was involved in studying software-defined receiver and developed silicon tuner and cellular RFICs.

Since 2014, he has been with the Department of Electronics Engineering, Kangwon National University, Chuncheon, Korea, where he is currently an Associate Professor.

His research interests include CMOS millimeter-wave/RF/ analog integrated circuits and RF system design for wireless communications.