1. Architecture and Operation of Asynchronous SAR ADC
The proposed 10-bit 10-MS/s asynchronous SAR ADC with input offset calibration consists
of a CDAC, a comparator, and a SAR logic including input offset calibration logic,
as shown in Fig. 1(a). The CDAC uses basically a V$_{\mathrm{CM}}$-based switching architecture which
consists of binary-weighted capacitors from C$_{8}$ to C$_{0}$ (8,9). In addition, it has an attenuation capacitor C$_{\mathrm{A}}$ so that the proposed
SAR ADC has a half rail-to-rail input voltage range (8). The attenuation capacitor C$_{\mathrm{A}}$ increases the size of the CDAC, but eliminates
additional reference voltages supplied to the CDAC for the implementation of the SAR
ADC with a half rail-to-rail input range. Meanwhile, the voltage of V$_{\mathrm{CM}}$
is generated to be the center voltage level between V$_{\mathrm{REFT}}$ and V$_{\mathrm{REFM}}$
through
Fig. 1. Proposed asynchronous SAR ADC (a) block diagram, (b) timing diagram
the supply of a differential analog input signal to the SAR ADC and differential operation
in the CDAC.
The proposed SAR ADC basically uses an asynchronous architecture to increase the sampling
rate without increasing the frequency of the external clock (8-10). The binary search operation of the SAR logic shown in Fig. 1(b) is sequentially performed by using the valid signal of the comparator, which informs
the completion of the comparison in the comparator. At the rising edge of EX_CLK,
which is the synchronous clock signal of the asynchronous SAR ADC, the sampling process
of the asynchronous SAR ADC is completed by the signal SAMPLE. Before the sample process
is complete, the signal SAMPLES, which controls the switch connecting the outputs
of the two CDACs (V$_{\mathrm{DACP}}$, V$_{\mathrm{DACM}}$) to each other, transitions
low before the signal SAMPLE. This is to reduce charge injection noise generated by
the sample switch. After the sampling process, the data conversion process for 10-bit
resolution begins. The operation of the CDAC and comparator is performed ten times
asynchronously by controlling the SAR logic to convert the sampled analog signal to
10-bit binary digital data.
Fig. 2. Concept of input offset calibration for ADC
After this data conversion process is finished, the asynchronous SAR ADC samples the
new analog input signal until the next rising edge of EX_CLK. The operation sequence
of the proposed asynchronous SAR ADC is independent of the duty cycle ratio of EX_CLK
because the proposed asynchronous SAR ADC uses only the rising edge of EX_CLK.
The four sub-capacitors (16${\cdot}$C$_{\mathrm{U}}$, 8${\cdot}$C$_{\mathrm{U}}$,
4${\cdot}$C$_{\mathrm{U}}$, 2${\cdot}$C$_{\mathrm{U}}$) of C$_{\mathrm{A}}$ for control
of the half rail-to-rail input voltage range and the 1${\cdot}$C$_{\mathrm{U}}$ (C$_{\mathrm{0b}}$)
of the CDAC are controlled to perform the proposed input offset calibration. Furthermore,
in the proposed input offset calibration mode, it is required that V$_{\mathrm{REFT}}$
and V$_{\mathrm{REFB}}$ having voltage levels of V$_{\mathrm{DD}}$ and V$_{\mathrm{SS}}$
are supplied as the differential analog input signals of the asynchronous SAR.
2. Input Offset Calibration using CDAC
Fig. 2 shows a graph of the transfer characteristics of the ADC. In general, the input offset
error of the ADC shifts the ADC’s transfer characteristic line down or up. Therefore,
if the ADC has the input offset error, the full digital code cannot be output for
the full range of analog input signals. The mismatch between the two input transistors
of the comparator can generate the input offset error in the SAR ADC. In addition,
the input offset error of the SAR ADC can be caused by the mismatch between the two
CDACs used for the differential structure of the CDAC. The proposed input offset calibration
corrects the transfer line of the SAR ADC to that of the ideal ADC by controlling
the attenuation capacitors in the CDAC used for the half rail-to-rail input voltage
range, as shown in Fig. 2.
Fig. 3 shows block and timing diagrams for generating control signals in the SAR logic for
each operation of the proposed input offset calibration. The control block for
Fig. 3. Control logic for input offset calibration (a) main block diagram, (b) timing
diagram
the input offset calibration operates in synchronization with the external clock EX_CLK
when the signal CAL for activation of the input offset calibration is high, as shown
in Fig. 3(a). At the first falling edge of EX_CLK after the signal CAL is applied for the input
offset calibration, the signals SAMP_CAL and SAMPD_CAL are activated for the operation
shown in the section A of Fig. 3(b). In the offset calibration mode, they are switched from the signals SAMP and SAMPS
for the normal data conversion mode, respectively, for the signals SAMPLE and SAMPLES.
In this section, the two reference voltages, V$_{\mathrm{REFT}}$ and V$_{\mathrm{REFB}}$,
are applied to the two bottom nodes of the differential CDAC instead of the two analog
input signals by the signal SAMP_CAL with a high state, as shown in Fig. 4(a). In this work, the voltage levels of V$_{\mathrm{DD}}$ and V$_{\mathrm{SS}}$ are
used for the two reference voltages, V$_{\mathrm{REFT}}$ and V$_{\mathrm{REFB}}$,
respectively. In addition, since the signal SAMPD_CAL is high, the CDAC generates
a V$_{\mathrm{CM}}$ having a center voltage level between the two reference voltages
by connecting V$_{\mathrm{DACP}}$ and V$_{\mathrm{DACM}}$ nodes. Fig. 5(a) shows the equivalent circuit of the CDAC in the section A.
Fig. 4. Operation of CDAC for input offset calibration (a) section A, (b) section
B, (c) section C
Fig. 4(b) shows the operation of the CDAC in the section B for the proposed input offset calibration.
The signal SAMP_CAL transitions low by the signal VCM_CAL generated in the SAR logic
for the input offset calibration in the section B. At the same time, all control signals
from S0 to S10, which are switch control signals for supplying V$_{\mathrm{CM}}$ for
the operation of the V$_{\mathrm{CM}}$-based switching CDAC, are transitioned high.
This section lasts while the signal SAMPD_CAL, which transitions low one cycle later
than the signal SAMPLE, remains high. In this section, the bottom nodes of the CDAC
are connected to the V$_{\mathrm{CM}}$ switches, and the top nodes of the CDAC, V$_{\mathrm{DACP}}$
and V$_{\mathrm{DACM}}$ nodes, are kept in a short circuit, as shown in Fig. 5(b). Through this operation, the CDAC outputs the voltage of V$_{\mathrm{CM}}$ while
discharging the charge of all capacitors of the CDAC. As a result, the input voltage
range of the comparator to
Fig. 5. Equivalent circuits of CDAC according to operation section for input offset
calibration (a) sample section of V$_{\mathrm{DD}}$ and V$_{\mathrm{SS}}$, (b) discharge
section of CDAC, (c) first comparison section of input offset voltage
determine the input offset voltage is secured to the center voltage level of the two
references without using an additional VCM generator for the CDAC.
After the signal SAMPD_CAL goes low and the signal CLKC_CAL goes high, the last step
of the input offset calibration, the section C, begins, as shown in Fig. 3(b). The signal CLKC_CAL is a control signal that activates the signal CLKC which is
a synchronous clock for the comparator. Fig. 4(c) shows the connection of the CDAC in this section. The operation of 32 consecutive
comparisons is performed on the voltage sampled by the V$_{\mathrm{CM}}$, and the
input offset voltage of the SAR ADC is sensed and saved at 16${\cdot}$C$_{\mathrm{U}}$,
8${\cdot}$C$_{\mathrm{U}}$, 4${\cdot}$C$_{\mathrm{U}}$, 2${\cdot}$C$_{\mathrm{U}}$,
and 1${\cdot}$C$_{\mathrm{U}}$ of the CDAC. As a result, a 5-bit control signal for
controlling the five capacitors for the input offset calibration is generated through
the operation of 32 consecutive comparisons. In order to exclude the influence of
input referred noise in the offset calibration process, the resolution of the proposed
offset calibration is determined by 1 least significant bit (LSB) of the SAR ADC with
10-bit resolution. Fig. 5(c) shows the equivalent circuit of the CDAC when the comparator performs the first comparison
for the input offset voltage in the section C.
Table 1 shows the connection status of the five capacitors controlled by the 5-bit control
signal for the input offset calibration. For the input offset calibration, the capacitors
for the input offset calibration of the positive and negative CDACs are switched to
the top and bottom references (V$_{\mathrm{DD}}$ and V$_{\mathrm{SS}}$) as opposed
to each other. When the first result of 32 comparisons for the input offset calibration
is high, the two 1${\cdot}$C$_{\mathrm{U}}$s of the positive and negative CDACs are
switched from V$_{\mathrm{CM}}$ to V$_{\mathrm{SS}}$ and V$_{\mathrm{CM}}$ to V$_{\mathrm{DD}}$,
respectively. Then, the comparator
table. 1. Control of capacitors of CDAC for input offset calibration
judges the voltage difference between the updated V$_{\mathrm{DACP}}$ and V$_{\mathrm{DACM}}$
nodes and outputs a second result. This result is also reflected in the switching
of the capacitors in the positive and negative CDACs for the input offset calibration.
When the comparator has an input offset voltage, consecutive reflections of the comparison
results of the comparator to the CDAC are performed so that the sum of the voltage
difference between V$_{\mathrm{DACM}}$ and V$_{\mathrm{DACP}}$ and the input offset
voltage of the comparator becomes zero. After the comparison of the comparator is
performed 32 times in total and the results are reflected in the switching of the
capacitors in the CDAC for the input offset calibration, the proposed input offset
calibration is ended. Meanwhile, other capacitors of the CDAC, except for the capacitors
for the input offset calibration, maintain the connection to the V$_{\mathrm{CM}}$
regardless of the 32 comparisons while performing the input offset calibration. After
performing the input offset calibration, the difference voltage between the V$_{\mathrm{DACM}}$
and V$_{\mathrm{DACP}}$ nodes is determined as the equivalent input offset voltage
of the SAR ADC.
Fig. 6 shows the simulation results of the proposed input offset calibration for the asynchronous
SAR ADC operating in the half rail-to-rail mode. In order to verify the proposed input
offset calibration, the simulation was performed by applying the input offset voltage
of 20 mV to the comparator. In addition, the differential analog input signals V$_{\mathrm{IP}}$
and V$_{\mathrm{IM}}$ of the SAR ADC with the half rail-to-rail input voltage range
are supplied with 3/4${\cdot}$(V$_{\mathrm{DD}}$${-}$V$_{\mathrm{SS}}$) and 1/4${\cdot}$(V$_{\mathrm{DD}}$${-}$V$_{\mathrm{SS}}$),
respectively. If there
Fig. 6. Simulation results of input offset calibration (a) offset calibration code,
(b) output voltages of CDAC, (c) output code of SAR ADC
is no input offset noise, the binary code of 10b'1111111111 is expected as a result
of the SAR ADC. However, before performing the input offset calibration, the SAR ADC
outputs the binary code of 10b’1111110101 due to the input offset voltage of the comparator,
as shown in Fig. 6(c). By performing the proposed input offset calibration, the offset calibration code,
CALP[4:0], which controls the five capacitors (16${\cdot}$C$_{\mathrm{U}}$, 8${\cdot}$C$_{\mathrm{U}}$,
4${\cdot}$C$_{\mathrm{U}}$, 2${\cdot}$C$_{\mathrm{U}}$, and 1${\cdot}$C$_{\mathrm{U}}$)
for the input offset calibration of the positive CDAC, is updated from 5’b00000 to
5b’01011, as shown in Fig. 6(a). Fig. 6(b) shows the difference voltage generated between the two nodes of V$_{\mathrm{DACP}}$
and V$_{\mathrm{DACM}}$ after performing the proposed input offset calibration. This
value is equal to the input offset voltage of the comparator preset to 20mV. The effect
of the input offset voltage is removed through the proposed input offset calibration,
so the SAR ADC outputs the binary code of 10b’1111111111, which is the ideal value
during normal operation, as shown in Fig. 6(c).
Fig. 7. Fabricated SAR ADC (a) chip photograph, (b) layout including calibration logic
for input offset calibration