1. Architecture

The designed ADC is based on ⁽¹³⁾, operating with two modes, conversion mode and calibration mode (Fig. 1). In the conversion mode, ADC receives the analog input V$_{\mathrm{IN}}$ and quickly performs 8-bit asynchronous SAR conversion, generating coarse 8 MSBs. Then, the residue integration is performed while receiving V$_{\mathrm{IN}}$. It accumulates the quantization error by estimating V$_{\mathrm{IN}}$ with the coarse 8 MSBs. After repeating the integration 2$^{5}$ times, the result is quickly converted again with the same SAR conversion used in the first step, generating fine 8 bits. During the residue integration step, a DSM loop simultaneously converts 1-bit output (E$_{\mathrm{j}}$) in parallel at each of 2$^{5}$ integration cycles. It helps to confine the amount of integrated residue and greatly relieves the requirement of amplifier gain. The total sum of two SAR conversion outputs and DSM outputs becomes the final digital output. In the summing process, the 8-bit output of the first SAR conversion are scaled up by 2$^{8}$. Since each DSM output affects the residue with a significance of the 5$^{\mathrm{th}}$ bit and the residue is then amplified by 2$^{3}$, the DSM output should be scaled by 2$^{8{-}5+3}$, or 2$^{6}$. Detailed circuit operation in the conversion mode is explained in Fig. 2. A DEM is applied to 5 MSB capacitors for averaging. The capacitors for 5 MSBs (C$_{\mathrm{S7:S3}}$) are implemented in a segmented capacitor array with each capacitance of 32C$_{\mathrm{DEM}}$. The 31 capacitors of C$_{\mathrm{S7:S3}}$ and a DSM capacitor (C$_{\mathrm{E}}$) form 32 identical capacitors for DEM. The DEM rotates the role of each capacitor during one full conversion of 32 cycles.

Fig. 3. Simulated INL with amplifier gain of (a) 1024, (b) 512, (c) 256.

The RI with DSM greatly relieves the required open-loop amplifier gain. Assuming that V$_{\mathrm{DD}}$ is the input conversion range, the maximum amplifier output (V$_{\mathrm{o,max}}$) during RI process confined by DSM operation becomes

Therefore, the maximum nonzero difference at the amplifier input during RI process due to the finite amplifier gain, A, is

which becomes the input-referred error at the amplifier input. Since the inter-stage closed-loop gain for the fine conversion can be reduced by the number of RI cycle (2$^{5}$), the maximum error at the amplifier output for the fine conversion is calculated to be

which should be less than 1 LSB of the 8-bit fine conversion, or $V_{DD}/2^{8}$. It leads to the requirement for A, as

Thus, the requirement for the amplifier gain is effectively reduced with factors of 2$^{-2}$ and 2$^{-5}$ by DSM and RI, respectively. Fig. 3 shows simulated INL for different amplifier gains, revealing the validity of the analysis.

In the calibration mode, a test input is self-generated by applying a known digital code. For the estimation of capacitor mismatch, two different combinations of digital codes representing the same amount of test input are prepared. Once the two digital codes are given, the residue integration is directly processed without the coarse conversion step. While one digital code provides an equivalent input, the other digital code performs the role of the coarse MSBs. The result of residue integrations is supposed to be 0 if the capacitors are perfectly matched. A nonzero residue is then converted through the subsequent fine SAR operation. Thus, the amount of capacitor mismatch among the sampling capacitors can be extracted from the ADC output code.

2. Calibration Algorithm

The calibration mode estimates the effect of mismatches of the eight MSB capacitors used for the input sampling during residue integration. The error is represented in a form of a ratio with the feedback capacitance ($128C_{LSB}$). Fig. 4 shows how to estimate the capacitance mismatch error. Let the dummy capacitor ($C_{DUMMY}$) of $4C_{LSB}$ be the reference. The capacitances, $C_{LSB}$, $C_{S0}$, $C_{S1}$, $C_{S2}$ and $C_{DEM}$ are identical if there is no error. To measure each capacitor error, two given calibration codes (CAL code$_{1}$, CAL code$_{2}$) are applied as the input and the estimated code for residue integration, respectively. The mismatch between $4C_{S0}$ and $C_{DUMMY}$ leads to a nonzero residue at the amplifier output after the first cycle of the residue integration, which is

After the 32nd integration, the output becomes

where $\alpha _{S0}=C_{S0}/C_{LSB}$. The $\alpha _{S0}$ becomes 1, or $V_{o[32]}$ is 0, if there is no mismatch error. Subsequent processing of $V_{o[32]}$ by the fine AD conversion reveals the information of mismatch error in a form of digital code. Defining $\varepsilon _{S0}$ to be the mismatch error in the capacitor $C_{S0}$,

Fig. 4. (a) Circuit configurations, (b) code sets for estimation of capacitor mismatch in the calibration mode.

The mismatch error for $C_{S1}$, represented by $\varepsilon _{S1}$, can be also derived in a similar way using the previously obtained $\varepsilon _{S0}$. Since the five MSB capacitors (C$_{\mathrm{S7:S3}}$) and C$_{\mathrm{E}}$ are averaged by DEM, the mismatch error for those capacitors can be represented by a single parameter with an averaged error. The capacitance ratios can be obtained as follows:

where $\alpha _{DEM}=C_{DEM}/C_{LSB}$, $\alpha _{S2}=C_{S2}/C_{LSB}$ and $\alpha _{S1}=C_{S1}/C_{LSB}$. The mismatch errors for capacitors C$_{\mathrm{S1}}$, C$_{\mathrm{S2}}$ and C$_{\mathrm{S7:S3}}$ are represented by $\varepsilon _{S1}$, $\varepsilon _{S2}$ and $\varepsilon _{DEM}$, respectively. The digitally estimated capacitance ratios ($\alpha _{DEM}$, $\alpha _{S2}$, $\alpha _{S1}$ and $\alpha _{S0}$) are used in the conversion mode by multiplying $\alpha _{DEM}$ to D$_{\mathrm{7:3}}$, $\alpha _{S2}$ to D$_{2}$, $\alpha _{S1}$ to D$_{1}$, $\alpha _{S0}$ to D$_{0}$ and $\alpha _{DEM}$ to E$_{\mathrm{31:0}}$, respectively. These multiplications can be simply implemented by addition of binary-weighted digitized errors ($\varepsilon _{S0}$, $\varepsilon _{S1}$, $\varepsilon _{S2}$ and $\varepsilon _{DEM}$).

To verify the calibration algorithm, we applied random mismatch to DAC which is comprised of unit capacitors. Fig. 5. shows simulated results when Gaussian statistics are applied to MSB capacitors with standard deviations of 0.02 and 0.05. The calibration noticeably improves linearity performance without any missing code. The conventional calibration schemes by only manipulating the final output code without affecting capacitor DAC could result in missing codes. However, the proposed calibration is applied to the coarse 8 bits and DSM bits before the summation with the fine 8 bits. Since the use of DSM provides a nonzero overlap between coarse 8 bits, there is no missing code in the calibrated output.

Fig. 5. Simulation results according to MSB capacitor mismatch applied to Gaussian statistics with standard deviation of (a) 0.02, (b) 0.05.