I. INTRODUCTION

As data traffic in the high-speed I/O networks has steadily increased, the demand for high-bandwidth transmission has also increased. However, the signal degradation is caused in the form of inter-symbol interference (ISI) by the bandwidth limitation in the copper-based channel as shown in Fig. 1, which gets much worse as data rates increase. To alleviate this problem, equalizer research in the high-speed I/O field has been steadily conducted, especially various continuous-time linear equalizers (CTLEs) and decision-feedback equalizers (DFEs) ^(1-12).

This paper proposes a receiver design that operates at data rates larger than 10 Gb/s in lossy FR4 traces with a low bit-error rates (BER) accomplished. We focus on not only improving the channel-equalization performance by adopting both an adaptive CTLE and an adaptive DFE but also reducing the area by excluding the usage of inductors such as a T-coil, a LC-VCO, and inductive peaking. Section Ⅱ describes the receiver architecture incorporating an adaptive CTLE and an adaptive DFE and suggests an offset-cancellation technique and a rectifying error-amplifier for the adaptive CTLE. Section Ⅱ also describes the DFE architecture that relaxes the timing constraint by using only a latch behind a current summer. Section Ⅲ describes the proposed adaptive 3-tap half-rate DFE and its implementation. Section Ⅲ also describes a digital low-pass filter with a hysteresis which is proposed to suppress the oscillation of the DFE tap coefficients and the related jitter. The performance measurement of the prototype chip is described in section Ⅳ. Finally, Section Ⅴ summarizes this paper.

II. RECEIVER ARCHITECTURE

Fig. 2 shows the receiver architecture. Channel equalization is performed by an adaptive CTLE and an adaptive DFE together. The equalized data is phase-detected by a clock-and-data recovery (CDR) and is deserialized by a serial-to-parallel block (S2P). The CDR is composed of a bang-bang phase detector, a charge pump, a loop filter, and a ring-VCO. To measure the receiver performance, a driver (DRV) is connected to the DFE output. The differential output of DRV is sent to an external sampling scope and a bit-error rate tester (BERT).

Fig. 3 shows the architecture of the adaptive CTLE. The high-frequency gain of the CTLE is adjusted by comparing the signals before and after a comparator ⁽¹⁾. However, a conventional CTLE used in ⁽¹⁾ seems to suffer from offset voltages of CLTE cells and an offset voltage between input signals (RXP and RXN). To cancel these offsets, another feedback is added to make the average of the positive CTLE output (EQP) and the average of the negative CLTE output (EQN) equal as shown in Fig. 3.

The CTLE cell is shown in Fig. 4. To perform offset cancelation, the resistance of the positive output load changes according to RCTRL. The minimum resistance is set to be about RDS || RDP and the maximum resistance is set to be RDP. To control the low-frequency gain, Rs is adjusted by a programmable control signal (EQ_DC). The output of a rectifying error-amplifier (ZCTRL) controls the capacitance of varactors ($C^{S}$) so that high-frequency gain is adaptively adjusted.

The source-follower rectifiers used in ⁽¹⁾ show a current consumption of about 1mA and a DC gain of about 0.88. Fig. 5 describes the rectifying error-amplifier which is an error-amplifier merged with a rectifier. This merged structure reduces the current consumption and enhances the DC gain. Stage 1 receives two pairs of differential signals from two high-pass filters located before and after the comparator. The four input transistors in Stage 1 are paired as {M1, M2} and {M3, M4}. The higher voltage of the input signals of each pair controls the output and Stage 1 plays a role of both a rectifier and an amplifier. Stage 2 amplifies the output of Stage 1 once more, generating ZCTRL.

Fig. 6 shows the simulated frequency responses for the 18-inch FR4 trace, the CTLE itself, and a conjunction of the trace and the CTLE. Considering receiver input capacitance, the channel attenuation is ${-}$15.67 dB at 5.2 GHz. And the CTLE performs high-frequency boosting to show ${-}$8.98 dB at 5.2 GHz.

CTLEs have several drawbacks. One of drawbacks is that high-frequency noise is also amplified while the high-frequency signal is boosted. Another drawback is that more than two stages of CTLEs are required for sufficient boosting. So, the bandwidth is inevitably degraded.

A DFE can complement the limited performance of a CTLE. A DFE determines whether the received data is '1' or '0' and utilizes this information to directly remove the post-cursor ISI without amplifying high-frequency noise as shown in Fig. 7.

However, the strict timing constraint for a DFE must be satisfied in order to remove the post cursor properly. Both a full-rate DFE and a half-rate DFE have the same timing constraint as follows ^(7,8):

In (1), $t_{CK2Q}$ stands for the clock-to-output delay of a flip-flop, $t_{SETUP.FF}$ stands for the setup time for a flip-flop, and $t_{FB}$stands for the feedback delay arising from a tap weighting and a current summer.

The timing constraint for a DFE is difficult to satisfy as a data rate increases (UI decreases). To relax the timing constraint, various methods have been proposed. One of them is replacing flip-flops next to the first flip-flop with latches ⁽⁴⁾ but the timing constraint of the first-tap feedback path is still not alleviated. Another is substituting a sample-and-hold (S/H) for a master latch in the first flip-flop ^(5,6). Others are merging a MUX ⁽⁷⁾ or a current summer ⁽⁸⁾ with a master latch in the first flip-flop.

To ease the burden of the timing constraint, the proposed architecture adopts the technique of using a slave latch behind a current summer but excludes other auxiliary circuits that perform a master-latch function such as a S/H ^(5,6), a merged latch and MUX ⁽⁷⁾, or a merged latch and current summer ⁽⁸⁾. Fig. 8 shows the illustrated block diagram of a 1-tap half-rate DFE using latches instead of flip-flops and shows the timing diagram. In Fig. 8(b), $t_{SETUP.LAT}$ stands for the time required for $De_{n}$ to be stored reliably by ‘Low’ of DCKB, $t_{DQ.LAT}$ stands for the input-to-output delay of a latch, and $t_{FB}$ stands for the feedback delay. The timing constraint in Fig. 8(a) is written as follows:

According to simulation results, $t_{DQ.LAT}$ is about 40 ps while the minimum shifting delay of a flip-flop, $t_{SHIFT.FF} \(=t_{CK2Q}+t_{SETUP.FF} \)$, is about 85 ps. Here, the minimum shifting delay of a flip-flop means the minimum input-to-output delay of a flip-flop ⁽¹³⁾. Since is measured about 10 ps, the left side of (1) is about 95 ps while that of (2) is about 50 ps. Thus, the timing constraint can be greatly mitigated by using only a latch after a current summer as shown in Fig. 8(a).

Due to the transparent nature of a latch, two issues need to be considered: the data racing and the recovered clocks’ misalignment. There is no data-racing problem because each of the two latches of Fig. 8(a) operates in either holding or sensing mode, respectively, with the opposite clock phases. The recovered clocks’ misalignment issue is addressed in the following section.

III. ADAPTIVE 3-TAP HALF-RATE DFE

Fig. 9 shows the proposed architecture of a 3-tap half-rate DFE. This structure is composed of the even-data path, the even-edge path, the odd-data path, and the odd-edge path. Both the even-data and odd-data paths use only latches instead of flip-flops to relax the timing constraint. However, both the even-edge and odd-edge paths still rely on the first flip-flops for optimal data-edge detection, which means that the edge clocks (XCK and XCKB) track data’s transition edges correctly. A current summer has a conventional structure ⁽³⁾ and a latch has a current-mode logic (CML) type. For the even data, the post cursors are removed by Do$_{n-1}$, $De_{n}$$_{n-2}$, and Do$_{n-3}$, corresponding to data before 1 UI, 2 UI, and 3 UI, respectively. For even edge, the post cursors are removed by Do$_{n-2}$, Do$_{n-3}$, and Do$_{n-4}$.

Fig. 10 shows an illustrated timing diagram of Fig. 9. For instance, the post cursors in the even data ‘G$_{T$_{8}$}$’ at T$_{8}$ are removed by ‘FT$_{8}$’, ‘ET$_{8}$’, and ‘DT$_{8}$’ at T$_{8}$, which correspond to $Do_{n}$$_{n-1}$, De$_{n-2}$, and Do$_{n-3}$, respectively. The post cursors in the even edge ‘GT9’ at T9 are removed by ‘F$_{T9}$’, ‘E$_{T9}$’, and ‘D$_{T9}$’ at T9.

IV. MEASUREMENT

The receiver test chip was designed and fabricated in 28-nm CMOS process. The RX layout and a die microphotograph are shown in Fig. 15. The active area of the chip is 980600 μm$^{2}$, where the adaptive DFE occupies 32080 μm$^{2}$ and the adaptive CTLE occupies 230100 μm$^{2}$.

Fig. 16 shows the test environment for measuring jitter, eye diagrams, and the BER of the data. A BERT provides a trigger clock for a sampling scope and a reference clock for a device under test (DUT) and generates PRBS patterns. ISI Board provides various lengths of FR4 traces. The BERT-generated PRBS pattern passes through ISI Board and becomes the input of the DUT. The data recovered by the DUT is analyzed by the sampling scope and the BERT.

Unless otherwise stated, all measurements are conducted with both the adaptive CTLE and adaptive DFE activated. PRBS 2$^7$ patterns are used and pre-emphasis is not applied during the measurements. The 1-V supply is used.

When using the 18-inch FR4 trace, no bit error was detected while transferring more than 10$^{14}$ data at 10.4 Gb/s but the BER increased as the data rate became larger than 10.4 Gb/s. When using the 12-inch FR4 trace, no bit error was detected while transferring more than 10$^{14} data at 11.2 Gb/s but the BER increased as the data rate became larger than 11.2 Gb/s.

Fig. 17(a) shows the measured eye diagram and jitter histogram at 10.4 Gb/s after the 18-inch FR4 trace. The measured jitter is as follows. DJ (deterministic Jitter) = 52.3 ps, RJ (random Jitter) = 1.07 ps, and TJ (total Jitter) = 66.9 ps. The measurement results show that ISI accounts for most of the DJ.

Fig. 17(b) shows the measured eye diagram and jitter histogram of recovered data, which is the output of the driver. Since the driver is driven by recovered clocks, it contains all the jitter components of the clocks. Of course, due to the jitter of the driver itself, the final jitter of the driver is expected to become larger. The measured jitter is as follows. DJ = 6.8 ps, RJ = 2.87 ps, and TJ = 46.1 ps. The operation of the equalizer and CDR reduces DJ by 45.5 ps but increases RJ by 1.8 ps.

Fig. 18(a) shows the measured eye diagram and jitter histogram at 11.2 Gb/s after the 12-inch FR4 trace. The measured jitter is as follows. DJ = 26.4 ps, RJ = 1.08 ps, and TJ = 41.1 ps. Fig. 18(b) shows the measured eye diagram and jitter histogram of recovered data. The measured jitter is as follows. DJ = 10.5 ps, RJ = 2.53 ps, and TJ = 45.1 ps.

Fig. 19 shows the measured jitter tolerance curves at 10.4-Gb/s and 11.2-Gb/s, respectively. The receiver has jitter tolerance of 0.266 UI and 0.322 UI at 10 MHz, respectively, with tracking bandwidths of about 2 MHz.

Fig. 20 shows the total power breakdown of the receiver measured at 11.2 Gb/s. The measured power consumption excluding the driver is 60 mW and the energy efficiency is calculated as 5.36 pJ/bit.

Table 1 summarizes the results of this receiver in comparison with other receivers having both a CTLE and a DFE. This receiver and the ones in ^(9,12) perform both CTLE and DFE adaptation. Compared to other receivers in ^(9-12), this receiver has a relatively very small BER (< $10^{-14}$).

V. CONCLUSIONS

This paper has described a receiver design that incorporates both an adaptive CTLE and an adaptive DFE. In the proposed CTLE, a merged rectifying error-amplifier reduces the current consumption and enhances the DC gain. Offset cancelation for the CTLE is performed by adaptively adjusting the load resistance of a CTLE cell. The proposed adaptive DFE relaxes the timing constraint using only a CML latch behind a current summer without other auxiliary circuits that perform a master-latch function. The DFE suppresses the oscillation of the DFE tap coefficients and the data level in the steady state utilizing a digital low-pass filter with a hysteresis. The receiver is fabricated in 28-nm CMOS process and occupies 980600 μm$^{2}$. The measured BER is less than $10^{-14}$ at 10.4 Gb/s for an 18-inch FR4 trace and at 11.2 Gb/s for a 12-inch FR4 trace, respectively, with both the adaptive CTLE and the adaptive DFE activated. In 11.2 Gb/s, the energy efficiency of the receiver is 5.36 pJ/bit.