I. INTRODUCTION

Many studies are currently being conducted to determine if scaling can be employed to build more devices on the same chip size. However, short-channel effects (SCEs) occur in transistors as a side effect of scaling ^(1-4). Therefore, a method of increasing gate controllability using high-k (HK)/metal-gate (MG) is being used as a solution of SCE. Nevertheless, HK materials are incompatible with poly-Si gates for reasons such as fermi-level pinning and phonon scattering ^(5-7). Thus, metal materials, such as TiN, TaN, and MoN, are used instead of a poly-Si for the gate ⁽⁸⁾.

Owing to using MGs, fermi-level pinning and phonon scattering are alleviated. Moreover, MGs have different work-functions (WFs) depending on the grain orientation, causing a WF variation (WFV), which affects transfer characteristics, such as threshold voltage ( $V_{\text {th }}$ ), subthreshold swing (SS), on-current ( $I_{\text {on }}$ ), and off-current ( $I_{\text {off }}$ ). Recently, many scholars have investigated transfer characteristics, especially $V_{\text {th }}$ shift by WFV ^(9-11). WFV is a semiconductor-manufacturing issue that needs to be addressed. However, a study on the effect of WFV on gate-all-around junctionless field-effect transistor (GAA-JLFET)-based capacitorless dynamic random-access memory (DRAM) has not been reported yet.

In this study, not only the variation in transfer characteristics but also the variation in memory performances due to WFV were investigated for a GAA-JLFET-based capacitorless DRAM with a Si/SiGe heterostructure ⁽¹²⁾. Numerous samples were simulated; in addition, to the best of our knowledge, it is the first time an analysis of a capacitorless DRAM from the WFV perspective is performed.

II. Device Structure and Simulation Method

Fig. 1 shows a three-dimensional (3-D) schematic view and cross-section view of the GAA-JLFET-based capacitorless DRAM. The Ge composition in SiGe of $0.2$ in the body region was determined from ref ⁽¹²⁾, which was an optimized value. The gate length $\left(L_{g}\right)$, underlap length ( $L_{\text {underlap }}$ ), nanowire radius $\left(R_{\text {nw }}\right)$, and gate dielectric $\left(\mathrm{HfO}_{2}\right)$ thicknesses $\left(T_{\mathrm{ox}}\right)$ were $70,15,10$, and $2 \mathrm{~nm}$, respectively, and the metal grain size $\left(G_{\text {size }}\right)$ was set to $10 \mathrm{~nm}$, a common measurement value ^(13,14). The role of the underlap structure was to reduce the electric field between the body and source/drain regions, which significantly affected the recombination/generation rate, which affected the improvement in retention time. For devices without WFV consideration, the body region was nearly depleted by the gate with a high WF of $5.0 \mathrm{eV}$ ⁽¹²⁾. However, the device considering WFV had a metal grain having WFs of $5.0$ and $4.4 \mathrm{eV}$ with $60 \%$ and $40 \%$ probability, respectively; it had a higher $I_{\text {off }}$ and a lower $V_{\text {th }}$ than the reference device. The doping concentrations of the source, body, and drain regions were $5 \times 10^{19}, 1 \times$ $10^{18}$, and $5 \times 10^{19} \mathrm{~cm}^{-3}$ ( $n$-type), respectively. The parameters for the proposed devices are listed in Table 1 .

The device design and analysis were performed using the Sentaurus 3-D Technology Computer-Aided Design (TCAD) simulation tool. The Sentaurus 3-D TCAD simulation tool was used to analyze the transfer characteristics and memory performances. Various physical models, such as the Shockley-Read-Hall recombination model, Fermi-Dirac statistical model, trap-assisted-tunneling model, Auger recombination model, nonlocal band-to-band tunneling model, doping-dependent and field-dependent mobility models, bandgap narrowing model, and quantum confinement effect were considered to obtain reliable results and maximize the simulation accuracy ⁽¹⁵⁾.

III. Results and Discussion

Fig. 2 shows the transfer curves of 200 samples of GAA-JLFET with the median data. To study the WFV effect, MoN MG, which has a high WF and can perform the memory operation of capacitorless DRAM, was used. The physical properties of various metals are summarized in Table 2 . The MoN comprises two types of grains, having different WFs depending on the grain orientation (e.g., WFs of $5.0$ and $4.4 \mathrm{eV}$ for $<110>$ and $<112>$, respectively). This phenomenon causes WFV in the GAA-JLFET, which fluctuates the transfer characteristics. Thus, the mean, standard deviation (SD), and relative SD (RSD) of the $V_{\text {th }}$ of the GAA-JLFET-

based capacitorless DRAMs was $0.766 \mathrm{~V}, 54.3 \mathrm{mV}$, and $7.09 \%$, respectively. RSD is SD divided by the mean and multiplied by 100 . In other words, a large RSD means that the SD is relatively large compared with the mean and the dispersion is large. The RSD has no unit, so it is a coefficient of merit used to compare the spread of

datasets with different measurement units. The RSD of the $S S, I_{\mathrm{on}}$, and $I_{\mathrm{off}}$ of the GAA-JLFET-based capacitorless DRAMs were $1.98 \%$ and $1.88 \%$, and $233 \%$ respectively, indicating that the variation in $I_{\text {off }}$ by WFV was large, which can be a problem for designing highreliability devices. Detailed transfer characteristics of the GAA-JLFET-based capacitorless DRAMs by WFV are summarized in Table 3 .

Among the 200 randomly generated samples, the memory performances were analyzed using two extreme cases with the highest and lowest $V_{\text {th }}$ of GAA-JLFETs

(Cases "A" and "B," respectively) are shown in Fig. 3(a). Case "A" shows low WF grains were concentrated near the source/body and drain/body junctions. The low WF grains lowered the potential barrier between the source/body and drain/body junctions; thus, the transistor was turned on easily. Therefore, it had a low $V_{\text {th }}$. Contrariwise, Case "B" shows high WF grains were located at source/body and drain/body junctions. The high WF grains increased the potential barrier between source/body and drain/body junctions; thus, the transistor required more gate voltage to be turned on. Therefore, it had a high $V_{\text {th. }}$. As shown in Fig. 3(b), the energy barrier

of Case "A" (i.e., red line) is lower than that of Case "B" (i.e., black line). Depending on the metal grain granularity, not only did transfer characteristics vary but also memory performances were affected by $V_{\text {th }}$. Fig. 4 (a) and (b) show the hole density distribution for states "1" and "0" of Cases "A" and "B." It shows that the distribution of hole density after write operation and erase operation, i.e., states "1" and " 0 ," when the electron potential energy is changed by WFV. For Case "A," compared with Case "B," the energy barrier is formed low at the source/channel and source/drain junctions due to the low wF distribution. Case "A" cannot form a physical barrier where holes can gather compared to Case "B." If the physical barrier is low, the hole density that can be confined becomes smaller, which in turn lowers the sensing margin among the memory performances. Case "B" has more holes than Case "A" in both states " 1 " and " 0 " [Fig. 4 (a)-(c)].

Fig. 5 shows the read currents at " 1 " and " 0 " States ( $I_{\mathrm{R} 1}$ and $I_{\mathrm{R} 0}$ ) as functions of gate voltage at the read operation ( $V_{\mathrm{G}_{-} \mathrm{R}}$ ). When $V_{\mathrm{G}_{-} \mathrm{R}}$ was $0.0$ and $0.2$ V, respectively, the GAA-JLFET-based capacitorless DRAM obtained an $I_{\mathrm{R} 1} / I_{\mathrm{R} 0}$ ratio of about $10^{2}$ and $10^{4}$, respectively, a much smaller value than the existing $I_{\mathrm{R} 1} / I_{\mathrm{R} 0}$ ratio of $10^{8}$⁽¹²⁾. The reason for this phenomenon is that the energy barrier is lowered by wFV, and the capability to confine the hole is weakened; thus, the hole density in the body region is lowered accordingly. As $V_{\mathrm{G}_{-} \mathrm{R}}$ increased, the $I_{\mathrm{R} 1} / I_{\mathrm{R} 0}$ ratio and sensing margin decreased because as $V_{\mathrm{G}_{-} \mathrm{R}} \mathrm{~ i n c r e a s e d , ~ a ~ c h a n n e l ~ w a s}$ formed, even at state “0.” The sensing margin is the

difference between $I_{R 1}$ and $I_{R 0}$. As shown in Fig. 5, the sensing margins of Cases "A" and "B" were $0.42$ and $0.34 \mu \mathrm{A} / \mu \mathrm{m}$ at $V_{\mathrm{G}_{-} \mathrm{R}}$ of $0.3$ and $0.5 \mathrm{~V}$, respectively. When considering the gate voltage where $I_{\mathrm{R} 1} / I_{\mathrm{R} 0}$ is the maximum, $0.0$ and $0.2 \mathrm{~V}$ should be applied. $V_{\mathrm{G}_{-} \mathrm{R}}$ at $0.0$ and $0.2 \mathrm{~V}$ have a high $I_{\mathrm{R} 1} / I_{\mathrm{R} 0}$ ratio but a very poor sensing margin. Therefore, $0.3$ and $0.5 \mathrm{~V}$ were selected as $V_{\mathrm{G}_{-} \mathrm{R}}$ because they did not only a high sensing margin but also easily distinguishable due to high $I_{R 1} I_{R 0}$ ratio. There were more hole densities in Case "B," but the sensing margin of Case "A" was $0.42 \mu \mathrm{A} / \mu \mathrm{m}$, larger than that of Case "B" $(0.34 \mu \mathrm{A} / \mu \mathrm{m})$, which was because $V_{\mathrm{G}_{-} \mathrm{R}}$ and hole density significantly affected the sensing margin. In summary, the storage number of holes was larger in

Case "B,"' but the sensing margin was higher in Case "A" due to the low gate voltage.

Fig. 6(a) and (b) show the $I_{\mathrm{R}}$ at " 1 " and " 0 " states and the sensing margin as functions of hold time when the $V_{\mathrm{G}_{-} \mathrm{R}}$ of Cases "A" and "B" was $0.3$ and $0.5 \mathrm{~V}$, respectively. The retention time is the time for the sensing margin to drop below $50 \%$ of its value ⁽¹⁷⁾. In a previous paper ⁽¹²⁾, a retention time of more than $10 \mathrm{~ms}$ was obtained when WFV was not considered. However, short retention times of $0.051 \mathrm{~ms}$ and $2.2 \mathrm{~ms}$ were obtained for Cases "A" and "B," respectively.

WFV is also detrimental to memory performances because the low WF of the metal grains directly affects the recombination/generation rate, which is a significant parameter of memory performances when located at the source/body and drain/body junctions [Fig. 7(a)]. In Case "A," owing to the lower WF than in Case "B," about 10 times more recombination occurred in the junction region based on the peak [Fig. 7(b)]. This caused the hole held in the body region to reduce more rapidly according to the hold time, reducing the retention time, which is the hole holding capacity. Consequently, compared with the performances of the GAA-JLFET-based capacitorless DRAM without WFV, GAA-JLFET-based capacitorless DRAM with WFV significantly degraded retention time because of metal grain variation. Without WFV, the current ratio was $10^{8}$, and the retention time was more than $10 \mathrm{~ms}$; meanwhile, with WFV, the current ratio was $10^{2}$ and $10^{4}$, and the retention time decreases to $0.051 \mathrm{~ms}$ and $2.2 \mathrm{~ms}$, respectively. This result shows that WFV impacts not only the transfer characteristics in GAAJLFET but also memory performances; in addition, it can adversely affect the reliability of the memory device.

IV. CONCLUSIONS

This paper presents transfer characteristics and memory performances variation caused by WFV in the metal gate of capacitorless DRAM cell based on a GAAJLFET. Due to the randomly distribution of metal gate grain orientation, 200 samples have different transfer characteristics such as $V_{\text {th }}, S S, I_{\text {off }}$, and $I_{\text {on. }}$ The RSD of $V_{\text {th }}, S S, I_{\text {off, }}$ and $I_{\text {on }} 7.09 \%, 1.98 \%, 1.88 \%$, and $233 \%$, respectively. In terms of the memory performances, the GAA-JLFET based capacitorless DRAM with considered WFV obtained $I_{\mathrm{R} 1} / I_{\mathrm{R} 0}$ ratio of about $10^{2}$ and $10^{4}$, respectively. This is a much smaller value than the previous experiment $I_{\mathrm{R} 1} / I_{\mathrm{R} 0}$ ratio of $10^{8}$ which does not take WFV into account. Additionally, long retention time more than 10 ms were obtained for retention time when WFV was not considered. However, take WFV into account, poor retention times of 0.051 ms and 2.2 ms were obtained, respectively, which differ by more than 5 to 100 times depending on the samples. Consequently, WFV has impact on the transfer characteristics in GAA-JLFET based capacitorless DRAM. It also significantly affects memory performances such as sensing margin and retention time.