1. Selecting wide Band Gap Material for p-type HTFET

In contrast to conventional SOI MOSFETs, the HTFET device with a nano trench structure on which a wide band gap material is deposited forms a high energy barrier between the source and the channel. The energy band diagram of channel region contains narrow energy barrier with wide band gap material as shown in Fig. 2. This barrier suppresses EHP generated in large quantities at high temperature and prevents excessive leakage current flowing by thermionic emission in the off state ^[16,17]. Since the HTFET shows a lower off-current than the conventional SOI MOSFET in a high temperature environment, it is possible to obtain an on/off ratio characteristic that classifies the logic level. As a result, it can be applied to CMOS logic circuits ^[18,19].

Fig. 3(a) is the transfer characteristics of p-type HTFET device and p-type SOI MOSFET with the same specifications. In the case of HTFET devices, simulations were carried out by applying various wide band gap materials to the nano trench region, respectively.

According to the results in Fig. 3(a), a conventional SOI MOSFET showed a high off-current of $-1.23\times 10^{-4}\,\mathrm{A}/\mu \mathrm{m}$ at 573 K. The on/off ratio value is 3.68, showing such small values that the logic values 0 and 1 cannot be distinguished in the digital logic circuit. The p-type HTFETs with various wide band gap material shows relatively large on/off ratio due to the blocking of thermionic emission at a high temperature. These results are similar with that of n-type HTFET in our previous work ^[15]. When various wide band gap materials are applied to the nano trench region of the HTFET, the height of the barrier formed in the valance band can be determined. As shown in Table 1, valance band barriers of various materials were estimated and applied to the simulation Fig. 3(b). As a result of the simulation shown in Fig. 3(a), it was confirmed that the off-current decreased exponentially in inverse proportion to the height of the barrier, as the thermionic emission equation ^[20]. When the 3C-SiC is used, it has an off-current of $-3.87\times 10^{-10}\,\mathrm{A}/\mu \mathrm{m}$, and the on/off ratio is $1.73\times 10^{4}$, which is sufficient to distinguish the logic of 0 and 1. The measured value shows a improvement of nearly 5,000 times from the on/off ratio of 3.68, in which a high temperature conventional SOI MOSFET was obtained. However, in the case of a material having a valance band barrier height higher than 3C-SiC, on-current decreases, and off-current limitation occurs in which off-current stays at a certain level without following the thermionic emission equation. Considering the designed operating range of CMOS logic ($\mathrm{V}_{\mathrm{DD}}=1.2\,\,\mathrm{V}$), there is a problem that $CeO_{2}$ has a lower on-current in on state due to the higher valance band barrier height than 3C-SiC. It shows on-current of $-1.29\times 10^{-7}\,\mathrm{A}/\mu \mathrm{m}$ for $\mathrm{CeO}_{2}$ and $-6.70\times 10^{-6}\,\mathrm{A}/\mu \mathrm{m}$ for 3C-SiC. Accordingly, the leakage current reduction by the barrier in the off state is similar, but the on/off ratio is reduced by about 100 times to $4.26\times 10^{2}$ compared to 3C-SiC with an on/off ratio of $1.73\times 10^{4}$ due to the on-current difference. Thus 3C-SiC would be more suitable as a wide band gap material.

Meanwhile, due to lattice mismatch and difference in thermal expansion coefficient with silicon, 3C-SiC requires a carbonization process of a silicon interface, a chemical vapor deposition (CVD) process and an annealing process in sequence in order to deposit 3C-SiC in the nano trench structure of the HTFET device proposed in this research ^[21]. Considering the fabrication of p-type HTFET, the influence of the charges at the interface between Si and 3C-SiC was investigated with TCAD simulation. According to previous result, it is possible to reduce the interface charge of 3C-SiC to $5\times 10^{10}\,\mathrm{cm}^{-2}$ through annealing process ^[22]. The simulation was performed while changing the interface trap charge density from $1\times 10^{13}\,\mathrm{cm}^{-2}$ to $5\times 10^{10}\,\mathrm{cm}^{-2}$.

When the trap charge is reduced from 1$\times 10^{13}\,\mathrm{cm}^{-2}$ to $5\times 10^{11}\,\mathrm{cm}^{-2}$, the on/off ratio of the device increases. In addition, when the trap charge is reduced from 5$\times 10^{11}$ to 5$\times 10^{10}\,\mathrm{cm}^{-2}$ over 5$\times 10^{11}\,\mathrm{cm}^{-2}$, the on/off ratio decreases, as shown in Fig. 5. This simulation results shows that the p-type device designed in this study for high-temperature operation has the highest on/off ratio of $1.68\times 10^{4}$ at 5$\times 10^{11}\,\mathrm{cm}^{-2}$. Furthermore, it was found that the value of 5$\times 10^{11}\,\mathrm{cm}^{-2}$ is the most suitable when considering the margin that reflects realistic process limits for reaching the maximum level of 5$\times 10^{10}\,\mathrm{cm}^{-2}$.

Therefore, it is possible to process an HTFET device having an interface trap charge of about $5\times 10^{11}\,\mathrm{cm}^{-2}$ at the 3C-SiC/Si interface and this value of $5\times 10^{11}\,\mathrm{cm}^{-2}$ was applied to device design in this study. The 3C-SiC/SiO$_{2}$ interface trap charge density values used in this paper have almost the same range as those measured in previous studies, $1\times 10^{11}\,\mathrm{cm}^{-2}$ ^[23].

Fig. 2. Energy band diagram for p-type HTFET.

Fig. 3. (a) Transfer characteristics; (b) channel energy band diagram of p-type HTFET with various wide band gap materials.

Fig. 4. Transfer characteristics with various interface trap charge densities.

Fig. 5. Transfer characteristics with various interface trap charge densities.}

2. Device Characterization and Optimization

We introduce improvement and optimization of p-type HTFETs based on the previously determined materials (3C-SiC) and interface conditions. The first optimization parameter is the body doping concentration. Range of body doping variation is from $1\times 10^{18}\,\mathrm{cm}^{-3}$ to $1\times 10^{16}\,\mathrm{cm}^{-3}$ as shown in Fig. 6. It was confirmed that the off-current decreased as the doping concentration of the body decreased. More specifically, the body doping concentration of $1\times 10^{18}\,\mathrm{cm}^{-3}$ has an on/off ratio of $6.57\times 10^{2}$, and $1\times 10^{17}\,\mathrm{cm}^{-3}$ has an on/off ratio of $4.75\times 10^{3}$. When doped with a concentration of $1\times 10^{16}\,\mathrm{cm}^{-3}$, the on/off ratio showed an improved on/off ratio value of $1.68\times 10^{4}$, and the device design was carried out with the corresponding value. As the body doping is lowered, the barrier of the hole existing between the drain and the channel increases, so the off current and on/off current ratio will be improved.

In the p-type HTFET device, a wide band gap material to prevent thermionic emission was deposited in a nano trench structure between the source and the channel. In this study, the thickness of nano trench was changed to check the leakage current caused by the horizontal electric field. In Fig. 7(a), the off current and on/off ratio improved as the thickness increased in the p-type HTFET as in the n-type HTFET. In Fig. 7(b), when the thickness of nano trench increased from 10 nm to 20 nm, the off-current decreased from $-8.93\times 10^{-10}\,\mathrm{A}/\mu \mathrm{m}$ to $-3.49\times 10^{-10}\,\mathrm{A}/\mu \mathrm{m}$. We applied direct tunneling physics to the simulation, and it was confirmed that the direct tunneling phenomenon did not affect the leakage current of the device even at the thickness of 10 nm. After that, at a thickness of 20 nm or more, the decrease in off-current was insignificant even as the thickness increased. However, while the on/off ratio increased from 10 nm to 30 nm, the on-current decreased at 40 nm thickness, and the on/off ratio decreased to $1.62\times 10^{4}$. Accordingly, it was found that the nano trench thickness of 30 nm showed an on/off ratio of $1.68\times 10^{4}$ and was the optimal thickness of the nano trench in the structure of the p-type HTFET device.

In this study, we were able to obtain a hole barrier height of 1.04 eV by applying a 3C-SiC material. Fig. 8 shows the effect of changing the hole barrier on the device's operating characteristics. When the barrier height is less than 1.04 eV, the leakage current is exponentially increased as the barrier height reduces due to the thermionic emission current characteristics. However, when the barrier height is 1.04 eV or more, the leakage current does not decrease significantly even when the barrier height was increased Fig. 8. In order to explain this off-current limiting phenomenon, a barrier value larger than 1.04 eV was arbitrarily set (1.34 eV) and the current characteristics were extracted. Fig. 9 shows the transfer characteristics of the device in which only the hole barrier was changed to 1.34 eV with the same other conditions.

In the high-temperature operation of the p-type HTFET, the off current is determined by the minority carrier electron. The energy band diagram in Fig. 10 explains why the leakage current is dominated by electrons. In the energy band diagram of the off current region indicated by the black line, electrons do not have sufficient energy barrier, which causes leakage current to flow. The red line in Fig. 10 is the simulation result of artificially increasing the electron energy barrier to 2.20~eV. If the energy barrier of electrons is increased with this value, the current component as shown in Fig. 11 can be obtained. If a better material other than 3C-SiC is applied to the p-type HTFET, it can be concluded that the electron barrier should be considered first. The effect of such a minority carrier has not been reported in the study of n-type HTFETs. Also, this result will be applied to the n-type HTFET as only the carrier type is changed.

Fig. 6. Transfer characteristics with various body doping concentration.

Fig. 7. (a) Transfer characteristics; (b) off current and on/off current ratio with various wide band gap material thickness.

Fig. 8. Off-current with hole energy barrier height variation.

Fig. 9. Transfer characteristics including hole current and electron current with 1.34 eV hole energy barrier.

Fig. 10. Energy band diagram with hole energy barrier height and electron barrier height variation.

Fig. 11. Transfer characteristics including hole current and electron current when hole energy barrier is 1.34 eV and electron energy barrier is 2.20 eV.

3. Verification of CMOS Logic in High Temperature

The CMOS logic gate structure has the advantages of higher control, lower power consumption, and improved integration than a single transistor ^[24]. In this chapter, we introduce the characteristics of CMOS inverter using the p-type HTFET proposed and optimized. Fig. 12 shows the configuration and operating voltage of CMOS inverter applied in this study. Based on the transfer curve characteristics of the device, the parameter was fitted as the characteristics of HTFET usable on HSPICE. Also, for configurating the CMOS logic, n-type HTFET which is previously researched was optimized to match with the p-type device studied in this study ^[15]. The fitting was performed in the same way for this n-type device. The n-type HTFET device constituting CMOS logic together with p-type has an off-current of $3.17\times 10^{-9}\,\mathrm{A}/\mu \mathrm{m}$ and an on/off ratio of $1.50\times 10^{4}$. As for the input voltage of CMOS logic, as shown in Fig. 13(a), a square wave with a pulse width (PW) of 1.4 ns, time rise (TR) of 0.1 ns, and down delay (TD) of 0.1 ns was applied with a period of 3.0 ns. Fig. 13(b) is the output voltage in which CMOS logic is configured with conventional MOSFET at 573 K. Fig. 13(c) is the output voltage in which the CMOS logic is configured with HTFET at 573 K. In the case of CMOS logic, which is designed with a conventional MOSFET in a 573 K high temperature environment, inverter characteristics for input signals is not achieved as shown in the Fig. 13. However, as a result of designing CMOS logic with the HTFET device designed in this study, it was possible to confirm the inverter characteristics for the input signal in a high temperature environment of 573 K. According to the result of Fig. 13(c), a pulse curve with delay is formed when rising because the characteristics of devices applied to logic circuits are influenced by the relatively small on/off ratio compared to the current characteristics of conventional MOSFETs operating at 300 K ^[25]. Nevertheless, through the verification of CMOS logic, the proposed p-type HTFET device demonstrated the switching characteristic that distinguish between logic 0 and 1 as a logic device during high temperature operation, and suggested the feasibility of applying it to a more complex logic circuit than CMOS logic.

Fig. 12. Schematic of CMOS logic inverter with HTFETs.

Fig. 13. Inverter logic simulation result: (a) input voltage; (b) output voltage of conventional MOSFET at 573 K; (c) output voltage of HTFET at 573 K.