1. UWB Radar Transceiver Architecture

Fig. 1 shows a simplified block diagram of the UWB radar transceiver which is composed of a transmitter, 4-channel receiver, and two cascaded DLLs for the sampling clock generation. The digitally controlled UWB impulse generator transmits the periodical UWB impulse waveforms, and then the receiver accepts the echo signal which has the round-trip time to the target. The received echo signal coming from the target is amplified by RF front-end amplifier stage and then splitted into the time- interleaved 4-channel analog signal processing (ASP) arrays via the active RF power splitter. In order to obtain the fast sampling rate for the high resolution, the receiver adopts both the equivalent time sampling (ETS) and the time-interleaved sampling techniques, whereas at each ASP channel the received signal is sampled with 0.2 ns interleaved clocks provided by the fine-bin DLL. Fig. 2 demonstrates how the virtually high speed sampling is achieved using ETS technique combined with the interleaved architecture. The pulse repetition time is 100 ns and the 125 times recursive samplings are done with the time shift of 0.8 ns for every sample. The clocks C1 - C125 of 0.8 ns interval are generated in the coarse-bin DLL, and in turn, four clocks F1 - F4 of 0.2 ns interval are also provided by the fine-bin DLL using Ck for 4 each channel.

For the mitigation of the DC offset noise in the ASP, which is amplified and usually saturates the ASP circuits, the 8-bit digital-to-analog converter (DAC) based DC offset calibration is used. Each receiver channel has a high-speed track-and-hold (T/H) circuit, an integrator, a sample-and-hold (S&H) circuit, and data-combining analog multiplexer (MUX) in the order. Moreover, not shown in Fig. 1, to compensate for the severe through-wall loss, the additional external PA and LNA are added for the radar gain enhancement.

Fig. 2. 4-channel time interleaved equivalent time sampling diagram.

2. High Resolution Radar Receiver Design

The RF front-end of the receiver consists of a LNA, 2-stage RF variable gain amplifier (RF VGA), an active power splitter, and track/hold circuit array for each channel. A noise cancelling common-gate common-source (CGCS) amplifier is used as the LNA both to obtain the wideband gain-noise matching and the single to differential signal conversion, as shown in Fig. 3. Since CS and CG paths have the amplitude and phase mismatches, the capacitive cross coupled structure is also adopted to reduce the mismatch and improve the noise figure. The Fig. 4(a) and (b) show the circuit schematics of the RF VGA and the 4-way (or channel) RF power splitter amplifier, respectively. The 2-stage RF VGA consists of two cascode amplifiers with the shunt CMOS transistor switch (M$_{5}$ and M$_{6}$) at the differential drain nodes of common source transistors for controlling the gain and enhance the linearity of the radar receiver. The simulated gain of the RF front end from LNA to RF VGA ranges from 16.9 dB to 37 dB at 1.2 GHz (center frequency), and the simulated NF are 3.0 and 8.6 dB for max and min gain conditions, respectively.

The amplified RF signal is equally splitted into 4 channels by the 4-way power splitter amplifier. The RF power splitter is a cascode amplifier with the four common gate transistor pairs (M$_{3}$ and M$_{4}$) for each ASP channel. The full gain and NF of the RF front end including LNA, VGA, and splitter, are 37 dB and 4.0 dB at 1.2 GHz, respectively. With the simple resistor load R$_{\mathrm{D}}$, the simulated 3 dB bandwidth is exceeding about 1.8 GHz. The fast time-varying UWB signal divided by the RF splitter is tracked and held at the T/H circuit, and amplified by the analog buffer amplifier and succeeding integrator. Fig. 5 shows the circuit schematic of the high-speed T/H circuit. The first stage of the track and hold circuit employs the shunt peaking load to extend the gain-bandwidth product. The T/H core adopts the switch source-follower structure, which allows the good linearity and the tracking bandwidth. The fast current path switching easily provides the high-speed sampling and holding performance. The required sampling clocks for each channel (track, hold, and sample) are generated by F1-F4 clocks coming from the fine-bin DLL ^[10].

The sampling clocks for 4-channels have the 200 ps time interval between the neighboring channels and the period of 800 ps. In order to realize the averaging and smoothing of the sampled signal, a conventional active RC integrator is employed in the radar receiver. During the averaging period, the clock number for the transmitter is not changed and the repeated sampling at the same time bin is performed. Hence the recursive sampled voltage is productively integrated so that the signal to noise ratio (SNR) is linearly improved by the number of repeated sampling times. The integration time is usually 25 us (250 integration times) and controlled by the external digital processing part. Also with the tuning of RC value of the integrator, the integrator gain can be variable from -9 dB to 45 dB. The DC gain of ASP is so large in the integrator that the amplified DC offset would be detrimental at the ASP output. Hence, 8-bit DAC is used for DC-offset correction at the input stage of analog integrator and controlled also by the digital part. The input-referred DC offset calibration range is up to 120 mV. At the final stage of ASP, the low speed S/H circuit and buffer amplifier is employed, and the integrated data is acquired and transferred to the external ADC included in the digital processing part. The DC offset mismatch between the 4-channel is compensated by individual optimization of DAC value for each channel. And addressed to the gain mismatch, the 1-dB step gain control in the integrator stage with the tunable resistor calibrates the gain of each channel and mitigates the effect of channel mismatch. The compensation with DAC and gain control is performed and optimized manually with the radar control S/W via SPI setting.

Fig. 3. Noise cancelling common-gate common-source LNA.

Fig. 4. Circuit schematic of (a) RF VGA; (b) RF power splitter.

Fig. 5. Circuit schematic of high speed T/H.

3. Radar Sampling Clock Generation using DLL

As shown in Fig. 6, in order to realize the equivalently high speed sampling or ETS, two cascaded DLLs are adopted as the timing clock generation circuit, which is locked to an external 10 MHz crystal oscillator ^[10]. Hence the pulse repetition interval (PRI) is 100 ns and the maximum detection range with no ambiguity is 15 m. Each DLL is composed of a voltage-controlled delay line (VCDL) cells, phase frequency detector and charge-pump with start-up circuit. The coarse-bin (CB) DLL generates 125 bin clocks (C1 - C125) with 0.8 ns interval. One of them is chosen by the bin selection MUX and used for triggering the digital impulse generator. The fine-bin (FB) DLL generates the four clocks (F1 - F4) with 0.2 ns time intervals, where C124 and C125 from the CB DLL are used as the reference clock and comparing clock, respectively. The generated four timing clocks from the FB DLL are fed to the individual T/H sampler of the four receiver channels, resulting in 0.2 ns equivalent sampling time resolution and 3 cm range resolution.

Fig. 6. Circuit schematic of high speed T/H.

4. UWB Waveform Generator

In contrast to the VCO based impulse generator, a digital pulse generator is employed due to its smaller chip size, the wider tunable range of the center frequency, and the lower power consumption ^[10,11]. Fig. 7 shows the simplified block diagram of the proposed pulse generator. The pulse generator consists of the variable time delay cells, D-flip/flop unit pulse generator array, a pulse combiner and shaper, and a final driver amplifier. The variable delay cell is an inverter, whose time delay is changed by controlling the current source. While the array of the delay cells provides the successively time delayed clocks to D-F/F array, the outputs from two neighboring D-F/F are injected into EX-OR and the unit pulse of duration ${\tau}$ is generated.

The center frequency is determined as 0.5${\tau}$, and the number of combined pulses decides the frequency bandwidth. Therefore, the center frequency and bandwidth are tunable by controlling the delay time and number of pulses. Considering the clock jitter noise, the source clock D(0) is coming from the DLL. If we assume that the jitter is 50 ps, the spectrum may be blurred about 500 kHz at 1 GHz center frequency, which doesn’t matter in respect of the target detection and spectrum regulation.

In order to minimize the side-lobes in frequency spectrum, a pulse shaping method is realized by the different and symmetrical amplifier gains in the pulse combiner stage, which enables the filtering and shaping of the UWB waveform without off chip filter component. And the spectrum change of the transmitter due to process and supply voltage changes are also scrutinized in the simulation. Fig. 8 shows the transmitter spectrum for each process condition (slow/typical/fast), and about 5 dB sidelobe magnitude change is observed also with the slight center frequency shift.

Fig. 7. Digitally synthesized impulse generator and output waveform.}

Fig. 8. Tx spectrum change due to process variation.}