I. INTRODUCTION

Tunneling field-effect transistor (TFET) has been widely studied to overcome the physical limitation in which subthreshold swing (S) of metal-oxide-semiconductor field-effect transistor (MOSFET) is not permitted to be below 60 mV/dec at room temperature ^[1-3]. However, its rather low on-state current (I$_{\mathrm{ON}}$) driven by band-to-band tunneling (BTBT) has been pointed out as a weak point. In order to enhance the current drivability of TFET, line tunneling field-effect transistor (LTFET) was proposed in the previous literature ^[4]. Also, it was reported that adopting gate with different workfunctions, dual-workfunction (DWF) gates, improved the current characteristics ^[5-9]. When DWG is applied to LTFET, the electrical characteristics vary greatly depending on important parameters such as the structure of the source region or the length of two gates, but there has been no detailed analysis on the optimization of this structure. Therefore, in this paper, optimal design of a DWF LTFET has been performed, and as the results, improvements of on-off current ratio (I$_{\mathrm{ON}}$/I$_{\mathrm{OFF}}$) and S have been achieved. The key solution lies in the engineering over the source-drain underlap in the DWF LTFET structure, which has been confirmed by series of numerical technology computer-aided design (TCAD) device simulations.

II. TUNNELING MODEL CALIBRATION

In order to calibrate the BTBT model using Sentaurus tools ^[10], the planar Si and SiGe TFETs are fabricated as shown in Fig. 1(a) and (b). In the case of Si TFET, SOI source implantation and drain implantation with As is used at the same conditions. For comparison, SiGe TFET consists of 40 nm thickness Si$_{\mathrm{0.7}}$Ge$_{\mathrm{0.3}}$ layers on SOI (100) substrates which are lightly p-doped (1 ${\times}$ 10$^{15}$ cm$^{-3}$) with 60 nm thickness and Si capping layer is grown on the SiGe channel and 200 nm thickness poly-Si gate and 3 nm SiO$_{2}$. The transfer characteristic of the fabricated Si and SiGe TFETs which have both 400 nm gate length and width are measured at the drain voltage (V$_{\mathrm{DS}}$) of 1.0 V.

Kane’s BTBT model is calibrated to the measured result of the fabricated Si and SiGe TFETs. The BTBT generation rates (G) per unit volume in this model are defined as

in the uniform electric field limit where F$_{0}$ = 1 V/m and P = 2.5 for indirect BTBT ^[10]. A of the pre-factor and B of the exponential factor are the Kane parameters while F is the electric field ^[11,12]. As mentioned above, several simulations are performed to fit the measured data by adjusting the A and B parameters. The A and B values are chosen as for optimal fit according to the results between the simulated and measured data Fig. 2. It can be seen that the log scale of transfer characteristics is well fitted from the results. The extracted A and B parameters of the BTBT model in Si TFET are 4 ${\times}$ 10$^{14}$ cm$^{-1}$·s$^{-1}$ and 9.9 ${\times}$ 10$^{6}$ V/cm, respectively. As SiGe TFET’s transfer characteristics, the A and B parameters of Ge can be extracted as 3.1 ${\times}$ 10$^{16}$ cm$^{-1}$·s$^{-1}$and 7.1 ${\times}$ 10$^{5}$ V/cm, respectively.

Fig. 1. Cross-sectional views of the (a) Si TFET; (b) SiGe TFET.

Fig. 2. Calibrated transfer curves of SiGe and Si TFET.

III. BASIC DEVICE STRUCTURE

Fig. 3 shows the basic device structure. The extruded source structure reduces the energy band bending of the pn junction where point tunnelling occurs, reducing the hump behavior. And the high WF gate-drain underlap reduces ambipolar current (I$_{\mathrm{AMB}}$) ^[4]. As drain is far from gate, the electric field applied to drain junction becomes weak. In this research, high WF is set to 5.10 eV and low WF is 4.06 eV, respectively.

Fig. 3. Basic structure of the device.

IV. SIMULATION AND RESULTS

To confirm the improved S and I$_{\mathrm{ON}}$/I$_{\mathrm{OFF}}$, numerical simulations are conducted by Sentaurus tools. Fig. 4(a) shows the drain current-gate voltage (I$_{\mathrm{D}}$-V$_{\mathrm{G}}$) characteristics of different WF and dual WF structures. Fig. 4(b) shows the BTBT generation rate at 0.7 V in this case. Single-high WF gate weakens the electric field applied to source, so less BTBT generation occurs and the total I$_{\mathrm{ON}}$ is decreased. And although point tunneling is reduced, line tunneling is also reduced, so it is difficult to expect better S. Single-low WF gate increases the electric field applied to source junction, so a lot of BTBT generation occurs and the total I$_{\mathrm{ON}}$ is increased. However, because of the low WF, point tunneling occurs even at 0~V, which increases the off-current (I$_{\mathrm{OFF}}$), and S gets worse. In case of dual gate with low WF and high WF, point tunneling at off-state is suppressed due to high WF gate and line tunneling at on-state is activated due to low WF gate, which improves S. The dual work function structure shows good electrical characteristics, but if point tunneling can be used in I$_{\mathrm{ON}}$ while suppressing I$_{\mathrm{OFF}}$, these characteristics can be improved further.

Fig. 5(a) shows the I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ characteristic according to the distance between high WF gate and drain. Fig. 5(b) shows the BTBT generation rate at -0.5 V in this case. As the drain underlap length increased from 0 nm to 10 nm, the hole tunneling is efficiently decreased and I$_{\mathrm{AMB}}$ is also reduced.

Fig. 6(a) shows the I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ characteristic according to the distance between high WF gate and source. Fig. 6(b) shows the BTBT generation rate at 0.7 V in this case. It is confirmed that I$_{\mathrm{OFF}}$ decreased as source underlap length increased from 0 nm to 10 nm. It shows that I$_{\mathrm{ON}}$/I$_{\mathrm{OFF}}$ is improved when the high WF gate underlap length is 3 nm to 5 nm compared to 0 nm to 2 nm. However, if the high WF gate underlap length is more than 6 nm, there is a possibility that I$_{\mathrm{OFF}}$ increases rapidly because of the process variation. Therefore, a gate underlap length between 3 nm to 5 nm is suitable. As a result, it is confirmed that I$_{\mathrm{ON}}$ can be increased by using point tunneling while suppressing I$_{\mathrm{OFF}}$.

Fig. 7(a) shows the I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ characteristic according to vertical tunneling length and Fig. 7(b) shows the BTBT generation rate at 0.7 V in this case. When the vertical tunneling length is 0 nm to 1 nm, line tunneling do not occur at V$_{\mathrm{GS}}$ = 0.7 V. This is because there is not enough space for line tunneling to occur. When the vertical tunneling length becomes 2\textasciitilde{}3 nm, line tunneling occurs as the gate voltage increases, and as a result, high I$_{\mathrm{ON}}$ can be obtained. However, when the vertical tunneling length is increased to 4 nm, the drain current at high voltage is rather decreased. This is because the width of the tunneling barrier increases as the depletion region increases.

Fig. 8(a) shows the I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ characteristic according to body thickness and Fig. 8(b) shows the BTBT generation rate at 0.7 V in this case. It is purpose to minimize the device size without causing performance degradation. First, in the case of I$_{\mathrm{ON}}$, even if the body thickness is reduced from 22 nm to 10 nm, there is no significant difference. On the other hand, it shows that I$_{\mathrm{AMB}}$ increases as body thickness decreases from 22 nm to 10~nm. However, this problem can be improved through drain underlap length. Through additional simulations, when the drain underlap length is 10 nm, it is confirmed that there is no increase in I$_{\mathrm{AMB}}$ even when the body thickness is reduced to 14 nm. As a result, the total body thickness is reduced from 20 nm to 14 nm.

Fig. 4. (a) Electrical characteristic of dual WF and different WF structures; (b) BTBT generation rate of dual WF and different WF structures at V$_{\mathrm{GS}}$ = 0.7 V.

Fig. 5. (a) Electrical characteristics by changing the distance between high WF gate and drain; (b) BTBT generation rate of high WF gate-drain underlap structures at V$_{\mathrm{GS}}$ = -0.5 V.

Fig. 6. (a) Electrical characteristics by changing the distance between high WF gate and source; (b) BTBT generation rate of low WF gate-source underlap structures at V$_{\mathrm{GS}}$ = 0.7 V.

Fig. 7. (a) Electrical characteristics by changing vertical tunneling length; (b) BTBT generation rate at V$_{\mathrm{GS}}$ = 0.7 V.

Fig. 8. (a) Electrical characteristics by changing body thickness; (b) BTBT generation rate at V$_{\mathrm{GS}}$ = 0.7 V.

V. VIABLE PROCESS INTEGRATION

Fig. 9(a)-(d) show the process of LTFET fabrication. Fig. 9(a) shows that the drain, body and source regions are sequentially grown through the epitaxy process ^[13,14]. Fig. 9(b) shows active patterning and device isolation process ^[15]. Fig. 9(c) shows that the vertical tunneling region is formed through Si-epitaxy. Finally, the proposed device fabrication is completed with gate oxide growth and gate patterning process as shown in Fig. 9(d).

Fig. 9. Fabrication process flow of the proposed device.

VI. CONCLUSIONS

Table 1 shows the optimized device parameters used for numerical simulation. Fig. 11 shows the I$_{\mathrm{D}}$-V$_{\mathrm{G}}$ characteristic of control device and optimized device (Fig. 10). A source and drain underlap on DWF LTFET is optimized. And a control device is the structure without high WF gate-drain underlap and low WF gate-source underlap in Fig. 3. By numerical simulations, it was confirmed that the source and drain underlap structure can improve the electrical performance at low voltage ^[16-21]. In particular, the distance between high WF gate and source is suitable to be 3 to 5 nm considering better I$_{\mathrm{ON}}$/I$_{\mathrm{OFF}}$ and the process variation.

Fig. 10. Optimized structure of the device.

Fig. 11. Electrical characteristic of control device and optimized device.