I. INTRODUCTION
Photoplethysmography (PPG) is a method that can detect the changes in blood volume
inside capillary vessels by measuring reflected or transmitted light among the light
irradiated on the human body. PPG can non-invasively measure heart rate or blood oxygen
saturation, so it is widely used in medical devices and wearable sensors.
LED is generally used to irradiate light to the human body in PPG applications. LED
driver generates the LED forward driving voltage that varies depending to the target
brightness of the LED. In general, the following features are required for LED drivers
for PPG applications. First, the drivers should control the current accurately, typically
in the range of a few mA to 100 mA for closed-loop operation with a readout circuit
[1]. Therefore, a calibration circuit for accurate current generation is essential [2]. A DC-DC conversion circuit is often required to generate various optimal turn-on
voltages of the LEDs, which varies depending on LEDs’ output spectrum. This is because
various LED lights such as red, green, and infra-red are used depending on the target
PPG application [3,4]. Finally, duty-cycling of the LED driving is also essential since the LED driver
is the dominant source of the power consumption in the PPG system [5].
However, to date, LED drivers for PPG systems have usually been implemented with simple
circuits such as voltage drivers [6] or current sources [7-9] only. These drivers adjust the current level or duty-cycle with control signals from
readout circuits, but they require several separate high supply voltages to drive
various LEDs.
In this paper, we present a high-efficiency LED driver for PPG applications that meets
previously mentioned requirements. For the current calibration, we propose NMOS resistor
array and RC-time constant based calibration technique. Pulse-width (PW) prediction
technique is also proposed which improves the settling time of the boost converter,
eliminating unnecessary power consumption during the loop settling. The article is
organized as follows. Section II describes the proposed driver circuits. Section III
presents simulation results and section IV concludes this paper.
II. CIRCUIT DESCRIPTION
1. The Proposed LED Driver Circuit
Top diagram of the proposed driver is shown in Fig. 1. First, NMOS resistor array (NRA) generated LED current ILED whose
dc quantity is defined by the control signal BI_LED and whose duty-cycle
is defined by the control signal BD_LED. The current control is performed
in all-digital way by adjusting the number of NMOS resistors in the array. The current
calibration code (CLB) is provided by the NRA calibrator which detect the process
variation of the circuit.
Fig. 1. Top structure of the proposed LED driver.
The PWM based boost convertor keeps VLED_C to Vref
by the closed loop operation and generates VOUTwhich is determined by
the ILEDand the LED’s I-V characteristics. The control loop consists
of a comparator, counter, digital loop filter (DLF) and pulse-width modulation (PWM)
signal (SW) generator. PW predictor initializes PWM control code (PWSW)
by calculating its initial code (PWPRD) with control inputs (BI_LED, BD_LED, BV_LED, and BR_LED) with proposed PW prediction technique. BV_LED and BR_LED are turn on voltage and equivalent resistance of LED, respectively, which
are typically obtained from the LED datasheet.
2. NMOS Resistor Array & Calibrator Circuit
Conventional current control circuit adopts digital-to-analog converter (DAC) [9] and reduces power consumption of current DAC by taking high current amplification
ratio with large output driving transistor. However, the output transistor experiences
a larger VGS change with wider output current range, and necessarily
needs a high VDS to remain in a saturation region. In addition, the
duty-cycling of the current sources needs additional settling time for analog node
voltages.
In this work, we use NMOS transistor as a resistor for direct output driving current
generation. The unit cell of NRA is shown in Fig. 2. The unit cell consists of k+1th stacked NMOS transistors and control
logics. Stacked transistor minimizes the area consumption while achieving high resistance
for a precise current control. The calibration code CLB[0:k] adjusts the number of
NMOS transistors turned on so that the current flowing from each unit cell is 1 mA.
DUTY signal is LED duty-cycling signal based on BD_LED input, and
collectively turns on and off all the NMOS resistors selected with CLB. One digit
of TI_LED controls one unit cell, and a total of 100-unit cells are
used to generate 1-100 mA current.
Fig. 2. Unit cell of NMOS resistor array.
The proposed all digital control not only eliminates static power consumption for
LED current generation but also facilitate accurate duty-cycle control. In addition,
since the VLED_C is fixed to Vref, the power efficiency
is maximized by minimizing the VDS of the transistors regardless of
the change in ILED or LED turn-on voltage.
The NRA calibrator circuit and its timing diagram are shows in Fig. 3 and 4. VLED_C is sampled in the CCLB with SPL signal and
discharged through NRA replica with DSC signal. NRA replica is designed to draw five
times smaller current than NRA unit cell to reduce power consumption. Then the capacitor
voltage VCLB and VCLB_REF are compared with the rising
edge of SEN with a clocked comparator. Therefore, RC-discharging time defined by CCLB
and NRA replica is compared to the half clock period(1/2⋅TCLKIN),
and the NRA resistance variation can be extracted.
Fig. 4. Timing diagram of NRA calibrator.
However, the comparison result also includes the impact of process variation of CCLB.
We adopt the look-up table (LUT) to remove it. First, the comparator output is integrated
to up/down counter and its k+1 most significant bits (MSBs) are used for CNTCLB.
Then, LUT translates CNTCLB to final NRA calibration code CLB. Fig. 5 shows the CNTCLB-CLB transfer curve for the LUT. It was designed by
linearly approximating each of the 5 process corners simulation results.
Fig. 5. Fitting curve for LUT design.
3. Boost Converter
Fig. 6 shows designed inductor-based boost converter circuit. The CMOS controlled rectifier
(CCR) and level shifter are used to increase power efficiency of the converter [10]. External inductor of 5 μH is used for LS whose series resistance
is 18.4~mΩ (Bourns, SRR6040A5R0Y). External capacitor of 200 μF is
used for COUT to minimize the change in ILED due to VOUT
ripple to within 1%. Therefore, since the minimum average ILED is 1
μA at 1 mA output current and 0.1% duty, the required DLF bandwidth for stability
should be very low, because of the low frequency output pole at VOUT,
which significantly increases the settling time.
Fig. 6. Circuit diagram of the boost converter.
The circuit diagram of the DLF is shown in Fig. 7 The proposed PW predictor, which will be described in the next section, provide calculated
target pulse width (PWPRD) for the fast settling. Since the integrator
value of DLF should be overwritten with PWPRD only when there is a difference
from the target value, whether to update the integrator value is determined by comparing
the current and past PWPRD. Loop filter output PWSW has
8-b resolution and the period of the PWM switching signal SW (TSW) is
256×TCLKIN.
Fig. 7. Circuit diagram of the digital loop filter.
The proportional gain α and the integral gain β of the DLF can be
determined as follows. First, the control-to-output transfer function Gvd(s)
can be obtained by setting the input voltage change ^vin(s)
to zero and solving the transfer function from the change ˆd(s)of
the duty cycle of SWOUT to the output voltage change ^vout(s)[11].
In (2) and (3), D is the duty cycle of SWOUT, RLED is the load resistance,
and Re is the effective resistance of MSW. The designed
boost converter operates in discontinuous conduction mode (DCM). In DCM, the voltage
conversion ratio of the boost converter is a function of the switch's operating duty
ratio, switching period, inductance, and load resistance [11]. The relationship between the current and voltage of an LED can be expressed by the
following equation [13]:
To derive the load resistance, LED is modeled as a resistor RLED with
a turn-on voltage Von as follows.
In (4), IS, VF and IF are the reverse bias saturation
current, forward voltage and forward current specified in the LED’s datasheet, respectively.
Lastly, due to the large capacitance of the output stage, it is considered as a 1-pole
system, and the pole frequency (ωp) can be calculated by the following
equation.
Therefore, the parameters α and β can be obtained by taking the bilinear
transform [12] in the continuous time Eq. (1).
4. PW Predictor
The MSW turn-on time (TSW,on) for the PWM control of the
boost converter is determined by the load current (ILED) and the output
voltage Vout. ILED are obtained from the control input
BI_LED.VOUT is derived as
VLED_C is converged to Vref with the loop operation,
and VON and RLED are obtained from the control input BV_LED and BR_LED. Therefore, by analyzing the boost converter
operation, target TSW,on at a given operating point can be calculated
and used for the fast settling of the loop.
TSW,on calculation process is as follow: First, since the voltage across
the inductor when the switch is turned on in the boost converter operation is input
supply voltage VIN, the maximum current iL,max flowing
through the inductor is derived as follows.
In (9), LS is the inductance of the inductor. If the voltage across
the inductor when the switch is off is VOUT-VIN, and the
time taken for the inductor to be completely discharged when the switch is off is
Tsw,off, the following equation can be derived.
Combining (9) and (10), we get:
The switch MSW operates only when the LED is turned-on, which is defined
by NRA turn on time (TDUTY,on) for LED duty-cycling defined by the control
input BD_LED. Therefore, during one cycle of DUTY, the MSW
operates n times, The n should be integer and is calculated as follows.
Therefore, the input average power (PIN,avg) is derived as:
And the output average power (POUT,avg) is:
In (14), ILED is the LED current and is defined by the control input BI_LED. IDC is a dc biasing current for CCR and level shifter in
the boost converter, which is obtained from SPICE circuit simulations. TDUTY
is the period of the LED duty-cycling (12×256×TCLKIN).
Finally, assuming that the average power supplied through the inductor LS
and the power dissipated from VOUT are the same, (13) and (14) are equal, we obtain TSW,on as follow
PW predictor performs digital signal processing of the Eq. (15) from control input (BI_LED→ILED, BD_LED→ TDUTY_ON, BV_LEDand BR_LED→VOUT) and circuit design parameters (LS,
VIN, IDC, TDUTY, TSW). Processed
output is 8-b PWPRD code, which generates TSW,on of PWPRD
×TCLKIN.
III. IMPLEMENTATION AND RESULTS
Proposed driver circuit is designed with 180-nm CMOS process. Digital signal processing
circuits including DLF and PW predictor are implemented with digital synthesis. For
the simple digital circuit implementation, we use the repeated subtraction method
[14] for the square root operation. Maximum simulated efficiency is 89% at 100 mA, 100%
duty with green LED (Osram, LGT676). From the LED datasheet and the Eqs. (5) and (6), Von and RLED are calculated as 1.84 V and 13 Ω,
respectively. The supply voltage (VIN) is 1 V. For CLKIN,
10 MHz is used. Vref is set to 200 mV. Output voltage (VOUT)
is 1.3-4.5 V with an input voltage (VIN) of 1 V through boost converter
control.
Fig. 8 shows simulated output current over process variation. The result shows the maximum
current error is 23% at FF corner, but it is improved to less than 0.5% with the proposed
calibration technique.
Fig. 8. Output current accuracy over process variation.
Fig. 9 shows the transient simulation result with 100~mA ILED and 100→0.1%
duty change at t=0. It takes unacceptably long time for VOUT to be settled
without the proposed technique, because the PWSW slowly decreases due
to the low loop bandwidth while the power consumption in the LED is dropped by 1/1000
with the duty change. By the proposed PW prediction technique, PWSW
code is immediately changed from 79 to 10 and the settling time of Vout
(<0.1% error) is greatly improved from 14.307 s to 124 ms.
Fig. 9. Transient simulation results of boost converter.
Tables 1 and 2 summarize the performance of the proposed LED driver for PPG and compare it with
previously published LED drivers and DC-DC converters. The proposed LED driver is
the only work that integrates several essential features for PPG applications, a wide-range
duty cycling, accurate current control and DC-DC converter supporting various types
of LEDs. The power efficiency of the boost converter is also comparable to other state
of the art works.
Table 1. Performance comparison (LED driver for PPG)
|
[15]
|
[16]
|
[17]
|
This work
|
Technology
|
0.18 μm
|
0.18 μm
|
0.13 μm
|
0.18 μm
|
Supply
Voltage
|
1.2/3.3 V
|
1/2.5 V
|
1.5/2.7 V
|
1 V
|
LED
Current
|
5 mA
|
0.1-
103.2 mA
|
50 mA
|
1-100 mA
|
LED duty
cycle
|
1%
|
10.24%
|
1%
|
0.1-100%
|
Current Calibration
|
N.A.
|
No
|
No
|
Yes
|
Integrated
DC-DC Converter
|
No
|
No
|
No
|
Yes
(w. Fast Settling)
|
Table 2. Performance comparison (DC-DC converter)
|
[10]
|
[18]
|
[19]
|
This work
|
Technology
|
0.35 μm
|
0.35 μm
|
0.5 μm
|
0.18 μm
|
Supply
Voltage
|
0.9-1.2 V
|
6-27 V
|
3.5-5 V
|
1 V
|
Clock Frequency
|
667 kHz
|
39 kHz
|
2 MHz
|
10 MHz
|
Maximum Efficiency
|
87%
|
90%
|
90.7%
|
89%
|