I. INTRODUCTION

As the data rate required by high-speed communication systems increases, its associated high-frequency channel loss is handled by high-performance equalization in the digital domain, which results in the demand for a high-speed ADC operating at tens of GS/s sampling rate. Since it is difficult to design a single-channel ADC to operate at such a high rate, multiple ADCs are typically interleaved in the time domain for high-speed ADC-based receivers ^[1,2]. However, a large interleaving factor of the time-interleaving (TI) ADCs increases the power consumption and design complexity of clock generation and distribution circuits. Therefore, it is important to increase the sampling rate of the sub-ADCs to minimize collateral issues caused by the massive time-interleaving technique.

SAR ADCs have been widely used for implementing the sub-ADCs because they are mainly composed of digital circuits, which consume very small static power and compact area in advanced CMOS processes. To increase the sampling rate of the SAR ADCs, various techniques such as multi-bit approximation per cycle ^[3], flash-assisted SAR ^[4], and loop-unrolling ^[5,6] have been presented. The SAR ADCs calculating multi-bit per cycle achieve a high sampling rate by reducing the number of cycles per conversion but consume high power due to hardware overheads in the capacitive digital-to-analog converters (CDACs) and the comparators. Flash-assisted SAR ADCs generate part of the entire bits with the flash ADC. However, mismatches between the flash and SAR stages degrade the signal-to-noise-and-distortion ratio (SNDR), and the power consumption of flash ADCs increases exponentially with its number of bits. Loop-unrolled SAR ADCs use multiple comparators to improve the sampling rate by excluding comparator reset operation from the cycle time. Furthermore, in ^[6], the sampling speed of the loop-unrolled SAR ADC can be further increased through the technique that controls the CDAC switching speculatively. However, this ADC does not include the comparator offset calibration, which requires a wider bandwidth for the sample-and-hold switches to compromise the settling errors due to larger parasitic capacitance. Furthermore, the oversized comparators require stronger driving capabilities of the preceding logic, which results in ADC performance degradation.

The SAR ADC proposed in this paper enhances the SNDR of the speculative loop-unrolled SAR ADC by calibrating comparator offsets. The foreground offset calibration relaxes the matching requirements and reduces the size and the power consumption for the serial comparators as well as the logic. The CDAC switching method is optimized to maintain the output common-mode (CM) level and the calibrated offset. Furthermore, the modified double-tail comparator reduces the kickback noise by shielding the feedthrough from the comparator output. The speculation structure, where the CDAC settling time is not included in the critical path, ensures that the addition of a calibration enable logic for calibration does not impede the ADC performance.

This paper is organized as follows. Section II reviews the speculative CDAC control technique ^[6], and Section III introduces the proposed comparator offset calibration technique. Section IV details the revised double-tail comparator structure and the CDAC switching method for the proposed offset calibration. Section V summarizes the measurement results, and finally, Section VI concludes this paper.

II. SPECULATIVE LOOP-UNROLLED SAR ADC

Fig. 1(a) illustrates the structure and timing diagram for a conventional loop-unrolled SAR ADC. For simplicity, Fig. 1 shows only a 1-bit conversion in single-ended. First, at the rising edge of the N$^{\mathrm{th}}$ comparator clock (CKC$_{\mathrm{N}}$), the N$^{\mathrm{th}}$ comparator (COMP$_{\mathrm{N}}$) compares the magnitudes of the input voltage (VIN) and the CDAC output voltage. After the comparison is finished, the SAR logic and the CDAC generate a voltage to be required for the (N+1)$^{\mathrm{th}}$ conversion, and the (N+1)$^{\mathrm{th}}$ comparator clock (CKC$_{\mathrm{(N+1)}}$) is triggered simultaneously. As mentioned in ^[6], the timing constraint is longer than the sum of the comparator clock-to-q and the longer of one between the CDAC settling time and the comparator clock generation. In general, the sum of the SAR logic delay and the CDAC settling time is longer than the delay for the comparator clock generation. Therefore, an additional delay is required for ensuring that the CDAC settling is completed before the comparator clock is triggered, which limits the sampling speed of the loop-unrolled SAR ADC and consumes unnecessary power.

As shown in Fig. 1(b), the architecture of the speculative loop-unrolled SAR ADC achieves a higher sampling rate than the conventional loop-unrolled SAR ADC. The CDAC settling of this architecture can be finished earlier than that of the conventional architecture by generating the (N+1)$^{\mathrm{th}}$ comparator input voltages from two CDACs before the N$^{\mathrm{th}}$ comparator produces its outputs (DP$_{\mathrm{N}}$ and DN$_{\mathrm{N}}$). The timing constraint of the speculative loop-unrolled SAR ADC is only the sum of the comparator clock-to-q and the comparator clock generation. Thus, compared to the conventional loop-unrolled SAR ADC, the overall conversion time of the speculative loop-unrolled SAR is reduced by the buffer propagation delay times the number of CDAC conversions (in this case, 5) of the ADC.

Although the ADC of ^[6] achieves a 1.5-GS/s sampling rate by applying this speculation technique, the absence of the comparator offset calibration causes SNDR degradation and the ADC performance. First, the large input transistor of the comparator causes a large parasitic capacitance of the CDAC output, which causes a decrease in the full-scale range of ADC. In the prototype of the proposed ADC ^[6], 32-unit capacitors (64 fF) show a full-scale swing smaller than half of the reference voltage, which means that the parasitic capacitance induced by the uncalibrated comparators is more than 64 fF. This results in a narrower input voltage difference at the comparator and degrades the SNDR, which depends on the input-referred noise of the comparator. Furthermore, it delays the conversion time of the comparator and reduces the sampling rate of the ADC. Secondly, the large total capacitance at the CDAC output causes the front-end sample-and-hold circuit to consume more power to satisfy the bandwidth and minimize the settling error. Finally, since the comparator clock generation logic and the selection logic (G and C at Fig. 1(b)) needs to be designed to drive the large size of the next comparator sufficiently, the propagation delays are lengthened as well as the conversion time, and the effect of the speculative technique is not maximized because the propagation delay still constrains the conversion time of the ADC. In the 28-nm CMOS process, the minimum propagation delay of a logic is longer than 5 ps and the buffer delay should be minimized while minimizing the load at the output of the comparators, which is around four buffer stages. Ideally, the overall conversion time reduction through speculative technique should be more than 100 ps, however, the large unit capacitor (2fF) and the comparator due to the absence of the offset calibration require increased logic size, thus, the next bit conversion happens far later than the CDAC settled. It results in the buffer delay in the timing constraint is not eliminated and the speculative technique is not maximized. Thanks to the foreground comparator offset calibration, the proposed speculative loop-unrolled SAR ADC achieves higher SNDR and sampling rate with smaller sizes of the comparators.

Fig. 1. A scheme and timing diagram for a 1-bit conversion in (a) the conventional loop-unrolled SAR ADC and in (b) the speculative loop-unrolled SAR ADC.

III. COMPARATOR OFFSET CALIBRATION FOR SPECULATIVE LOOP-UNROLLED SAR ADC

In this work, a foreground comparator offset calibration technique for the speculative ADC is implemented to mitigate the offset mismatch and to improve the ADC performance. Fig. 2 shows the environmental setup for the foreground offset calibration. During the calibration phase, zero differential input voltage is applied to the input and the CDAC switching is disabled. Unlike conventional loop-unrolled SAR ADCs, the CDAC settling is not included in the critical path of the speculative loop-unrolled SAR ADC as mentioned in the previous section. Thus, the additional logic delay by the enable signal, EN, does not affect the conversion speed. In this configuration, all comparators compare the zero-differential input, and their outputs are determined by the sign of the offset. Then the calibration code searching operation is performed at a low frequency to avoid insufficient conversion time due to metastability. The ADC output is gathered by the logic analyzer and the resistive DACs (RDACs) are controlled so that all comparator outputs have 50% distributions for 0 and 1 through the inter-integrated circuit (I$^{2}$C) protocol. However, the speculative loop-unrolled SAR ADC involves selecting one of the two differential CDACs according to the output of the previous comparator. Therefore, a dedicated algorithm for calibrating both cases where the CDAC$_{\mathrm{A}}$ or the CDAC$_{\mathrm{B}}$ is selected is required. Fig. 3 shows the foreground offset calibration flow chart for the speculation technique. Four 6-bit calibration codes control the RDAC for the input branches of the comparator. The RDAC codes for the MSB comparator offset calibration are configured to DCAL$_{\mathrm{1 \_ AP}}$= 6’b111111 and DCAL$_{\mathrm{1 \_ AN}}$= 6’b000000 to force the output to one. After that, the differential calibration code decreases until the probability for the output of 0 is higher than that for 1. For the rest of the comparators (which need to be calibrated for CDAC$_{\mathrm{A}}$ as well as CDAC$_{\mathrm{B}}$ for loop unrolling), each of the two branches is selectively activated by setting the RDACs for the previous-bit comparator to be fully steered to produce a constant (either high or low) output; For example, the inputs of the RDACs for the (M-1)$^{\mathrm{th}}$ comparator are set to DCAL$_{\mathrm{(M-1) \_ AP}}$=111111 and DCAL$_{\mathrm{(M-1) \_ AN}}$=000000 to force the (M-1)$^{\mathrm{th}}$ comparator outputs to be always high. Then, only one of the two branches in the M$^{\mathrm{th}}$ comparator is always activated, and its calibration code can be found by the same process for the MSB comparator. After the calibration codes for both branches in the 2$^{\mathrm{nd}}$ comparator are determined by this process, the sequence is repeated for the rest of the bit. To verify the offset calibration so that the output probability is 50%, the calibration is performed 65,536 times for each branch of the comparator.

Fig. 2. Proposed SAR ADC architecture and environment setup for the foreground comparator offset calibration.

Fig. 3. Foreground comparator offset calibration flow chart.

IV. DESIGN IMPLEMENTATIONS

Fig. 4(a) shows the schematic of the CDAC of the proposed SAR ADC. To implement the speculative technique, the switching logic of the CDAC is designed with true-single-phase-clock (TSPC) flip flops. As soon as the front-end bootstrapped switches open, the comparator decides the most-significant bit (MSB), and the TSPCs connected to the 4C$_{\mathrm{U}}$ switch after as much as the propagation delay of TSPC reset-to-set or set-to-reset switching to implement the CDAC output for the next comparison after the MSB. After that, the subordinate CDAC outputs are generated by the TSPC after as much as the TSPC clock-to-q delay. As shown in Fig. 4(b), the front-end bootstrapped switch samples the input signal and holds the signal for conversion. In the prototype ADC ^[6], the bandwidth of the front-end switch is limited due to the large total capacitance, which is about 128 fF. However, the proposed speculative SAR ADC has smaller total capacitance at the output of CDAC due to the foreground comparator offset calibration and the modified CDAC switching method. The total capacitance at the output of the CDAC is about 36 fF including 16-unit capacitors (16 fF), which is 3.3 times smaller than ^[6]. The simulation results in Fig. 4(c) shows that the total harmonic distortion (THD) is at least 10 dB lower than the prototype with the 300–800 mV input common-mode voltage. Even though the prototype shows that the THD is 10 dB lower than the 6-bit resolution requirement (-37.88 dB) with 128-fF loading, the excessive CDAC output loading forbids the proposed ADC to be time-interleaved because the preceding driver stage would have a limited bandwidth.

The speculation technique requires a dedicated CDAC switching process ^[6]. In ^[6], to mitigate the increase of the switching energy due to the additional CDAC, the two differential CDACs are re-defined as the four independent CDACs. However, the switching method varies the input common-mode (CM) level of the comparator depending on the combination of the CDACs selected in each cycle, which deteriorates the offset characteristics of comparators.

Therefore, this paper modifies the switching method to preserve the CM level and improve the comparator offset (Fig. 5). The switching method is based on ^[10] and has minor modifications for speculative operation. In ^[6], the maximum input common-mode level variation is 1/4V$_{\mathrm{REF}}$ in the MSB-1 conversion as shown in Fig. 6, however, the output CM levels of the proposed CDAC switching are maintained across the conversion digits and the common-mode voltage variation of the proposed ADC is only 1/32V$_{\mathrm{REF}}$ in the LSB conversion, suppressing dynamic offset fluctuations due to CM shifts.

To speed up the sampling rate of the proposed speculative SAR ADC further, the comparator structure is changed from the strong-arm comparator ^[6] to the double-tail latch-type comparator. As mentioned in ^[7], the double-tail comparator shows much faster clock-to-q delay than the strong-arm comparator in the lower input common-mode voltage. Since the high input common-mode voltage limits the bootstrapped switch due to the difficulty of discharging the high gate voltage, the double-tail latch-type comparator is more compatible in terms of the speed and the sample-and-hold circuit. Fig. 7 shows the modified double-tail comparator for the proposed SAR ADC. The comparator has four input ports, M$_{\mathrm{0\hbox{-}3}}$, to receive signals from the two differential CDACs. The modified double-tail architecture originates in ^[7] with minor changes for the kickback noise reduction by clocking the input transistor through their drain path ^[8,9]. Compared with the conventional structure, the modified comparator has lower kickback noise because the only source of the clock-feedthrough is the selection paths (S$_{\mathrm{PA\hbox{-}B}}$, S$_{\mathrm{NA\hbox{-}B}}$), and the clock-feedthrough from the output transitions of the pre-amplifying stage (X$_{\mathrm{N}}$ and X$_{\mathrm{P}}$) is shielding by the cascoded transistors, M$_{\mathrm{4\hbox{-}7}}$. According to the kickback simulation, the differential kickback noise is attenuated by more than 4 times from 6.63 mV to 1.64 mV. In other perspective, the proposed structure shows characteristics similar to that of the conventional one in terms of clock-to-q delay, power consumption, and input-referred noise (IRN) expect the offset voltage. Since the 550-mV input common-mode voltage of the proposed SAR ADC is chosen to compromise between the clock-to-q delay of the comparator IRN to maximize the SNDR of the proposed ADC, the offset voltage increment is around 20% compared to the conventional comparator, which can be calibrated.

As mentioned in Section 3, the calibration is performed in all the input branches for the speculative techniques. As shown in Fig. 7, the offset calibration is implemented with the current calibration branches, M$_{\mathrm{C0\hbox{-}7}}$, and the widths of transistors for calibration are 1/8 of that for the input branches, M$_{\mathrm{0\hbox{-}7}}$, to achieve a target resolution for the offset calibration. Monte Carlo simulations prove that the input-referred offset standard deviation at 550-mV input common-mode voltage is 18.9 mV (3.15 LSB). Using 6-bit RDAC, the offset for each branch is calibrated with a resolution of 1.17 mV and a maximum range of ${\pm}$75 mV to cover ${\pm}$4${\sigma}$ range of the offset.

Fig. 4. (a) Schematic of CDAC of the proposed ADC; (b) schematic of the bootstrapped switch; (c) simulation result of the total harmonic distortion of the bootstrapped switch at various input common-mode voltage for 36-fF and 128-fF output loading.

Fig. 5. 3-bit example of CDAC switching method for the proposed SAR ADC.

Fig. 6. Variation of the comparator input common-mode level for conventional[6]and proposed switching methods.

Fig. 7. (a) Schematic of comparator of the proposed ADC; (b) simulation result of the clock-to-q, the offset voltage, the input-referred noise (IRN) and the power consumption of the double-tail latch-type comparator for the various input common-mode voltage.

V. MEASUREMENT RESULTS

Fig. 8 shows the die photograph and the layout of the proposed SAR ADC, which is implemented in a 28-nm CMOS process. The active area of the ADC core is 44${\times}$41 ${\mu}$m$^{2}$, excluding the 22 6-bit RDACs and I$^{2}$C slave register array as shown in the on-chip core in Fig. 2. The total core power consumption of the proposed SAR ADC is 6.2-mW from a 1.2-V supply voltage excluding the power consumption in the RDACs. Fig. 9 shows the power breakdown of the ADC. Fig. 10 shows that the SNDR is improved by 3.3 dB after calibration at the 2-GS/s sampling rate for the 994-MHz Nyquist input frequency with a 770-mV$_{\mathrm{pp}}$ input swing at a 550-mV common-mode level. Fig. 11 shows the SNDR measurement results versus the input amplitude at the Nyquist input frequency, the input frequency, and the sampling rate of the proposed SAR ADC at the Nyquist input frequency. Thanks to the smaller CDAC output total capacitance and the faster double-tail comparator, the proposed SAR ADC achieves 1.3x faster 2-GS/s sampling rate and a maximum 36.7-dB SNDR at 1.8-GS/S, where the highest SNDR in the prototype ^[6] is only lower than 32-dB SNDR. Even at 2-GS/s, the effective number of bits (ENOB) is 5.21 bits and decreases as the input frequency increases. Table 1 compares the performance of the proposed ADC with the state-of-the-art works. The proposed ADC improves the performance of the speculative loop-unrolled SAR ADC significantly thanks to the comparator offset calibration and provides the highest sampling rate among the single-channel loop-unrolled SAR ADCs.

Fig. 8. Die photograph and layout of the proposed SAR ADC: (a) ADC core; (b) RDAC; (c) I2C slave register array.

Fig. 9. Power breakdown of the proposed SAR ADC.

IV. CONCLUSIONS

This paper presents a high-speed single-channel speculative loop-unrolled SAR ADC with a foreground comparator offset calibration. The speculative technique is further maximized bythe foreground offset calibration compatible with the speculative technique and improves the performance of the proposed SAR ADC with a smaller CDAC output loading. The CDAC switching method preserves the output CM level to suppress the dynamic offset drift. The modified double-tail comparator reduces the kickback noise and enhances the sampling rate by a faster comparator clock-to-q delay. The proposed single-channel 6-bit ADC is fabricated in a 28-nm CMOS process. The proposed SAR ADC achieves 36.7/32.5-dB SNDR with 5.8-mW power consumption at a 1.8-GS/s sampling rate and 33.1/29.9-dB SNDR with 6.2-mW power consumption at a 2-GS/s sampling rate, respectively.