I. INTRODUCTION

The frequency dividers with high-division ratios for converting high-frequency radio frequency (RF) signals to a lower frequency that can be easily and reliably used as the input port of a phase locked loop (PLL) circuit, are the subject of intense ongoing research due to their practical importance.

A true single-phase clock flip-flop (TSPCFF) based C-band divider has been reported for programable wide-band application. The TSPCFF provides reasonably fast, compact size, and no static power and requires only one phase of the clock. However, signal needs to propagate through three gates per input cycle, needs full swing complementary metal oxide semiconductor (CMOS) inputs, and dynamic flip-flop can fail at low frequency due to leakage, as various nodes are floating during different clock phases and output states ^[1].

A 26 GHz static current mode logic fip-flop (CMLFF) based divide-by-32 divider with an n-channel metal-oxide-semiconductor (NMOS) cross-coupled latch by sequential digital logic has been reported for wide-band application. The signal only propagates through two current mode logic (CML) gates per input cycle and accepts CML input levels in the CMLFF. Larg\underbar{e} size and dissipating static power are unavoidable. The requirement for differential input and tail current biasing are additional disadvantages ^[2]. K-band ^[3] and W-band ^[4] divide-by-3 dividers using inductors on NMOS cross-coupled latch have been proposed as injection-locked frequency dividers (ILFD) for higher frequency applications. This design features a very large inductor which at high frequencies is difficult to accurately model and uses an unavoidable large fraction of the die. A V-band static divider not using an inductor has been reported to reduce the die area and avoid the model inaccuracy associated with high frequency inductors ^[5]. P. Fahs has presented a two-stage ring oscillator based on p-channel metal-oxide-semiconductor (PMOS) cross-coupled pairs that can operate from 1.82 GHz to 10.18 GHz without using any inductor. Local positive feedback is used to achieve (1) steady oscillation at low current consumption and a wide range of frequency tuning ^[6].

In this paper, a pair of buffers is connected to the P. Fahs' two-stage PMOS cross latch circuit, to provide the output signal with (1) an improved stability against load impedance change and (2) an enhanced harmonic-power generation ability for high DC supply voltage. The output is further fed back to the input to form a divide-by-2 divider unit. By cascading 6 dividers units, a divide-by-64 divider is realized. When the DC supply voltage is less than 1.6 V, it exhibits an exact 64 digital division operation for input signals up to 9 GHz. As the voltage increases further, a few limited-range frequency bands are realized between 2 GHz and 27.113 GHz that operate as ILFDs with their own division ratios. The division ratio increases up to 528, which is much higher than previously reported in the literature. Overall this paper demonstrates a unique synergetic operation between multi-band ILFD and multi-band divider circuit, revealing behavior unanticipated by computer simulation but validated through results from the fabricated die test.

II. CIRCUIT AND PERFORMANCE

Fig. 1 shows the schematic of the divide-by-2 divider unit circuit proposed in this paper. To get a stable division action immune from variations in the load impedance, and promote harmonic generation at large bias, a pair of inverting buffers is inserted in the feedback path of the PMOS cross-coupled flip-flop.

The basic divide-by-2 divider circuit operates as an independent circuit when the load impedance connected to the output is sufficiently large, but if the output impedance is not large enough, the output current supplied from the output terminal is not sufficient, and the states of the MOSFETs (MN1, MN2) at the input terminal cannot be reversed. Therefore, a pair of inverting buffers are added as shown in Fig. 1, which can supply enough current to invert the states of MN1 and MN2 by using feedback to ensure stable operation even at low load impedance. A divide-by-2 divider-unit circuit is created by adding the inverting buffer pair connected to the CMOS cascode with MP5-MN5 and MP6-MN6 to the output terminal of the basic divide-by-2 divider circuit. Since the output voltages are inverted by the inverting buffers, the feedback input terminals are connected in the opposite way compared to a typical divide-by-2 divider circuit.

The sequences 1, 2, 3, and 4 in Fig. 2 describe the detailed circuit behavior during clock transitions. The sequential digital-logic timing analysis, as indicated inside the bracket ( ) positioned at the bottom of the common nodes in Fig. 1.(b), is confirmed by the timing simulation in Fig. 2.

In sequence 1, when ${\rm CLK}=1$ and ${\rm CLKB}=0$, MN7 is conducted and MN8 is blocked. At this time, since ${\rm D}=1$ and ${\rm DB}=0$, MN1 conducts and MN2 is blocked, and thus MP1 is blocked and MP2 is conducts, resulting in the gate voltages MP1Gate and MP2Gate of MP1 and MP2 staying in state 1 with ${\rm MP1Gate}=1$ and ${\rm MP2Gate}=0$, respectively.

In sequence 2, when CLK and CLKB are toggled from state 1, MN7 is blocked and MN8 is conducting, resulting in a logic state of ${\rm D}=0$, ${\rm DB}=1$. Therefore, MN1 is blocked, MN2 is conducting, and then MP1 is blocked and MP2 are conducting, resulting in state 2 with ${\rm MP1Gate}=1$ and ${\rm MP2Gate}=0$.

In sequence 3, when CLK and CLKB are toggled from the state 2, MN7 conducts and MN8 is blocked, but D and DB maintain the logic state in 2. MN1 and MN2 also maintain their previous states, but since MN7 has been changed to a conducting state, it becomes the state 3 with ${\rm MP1Gate}=0$ and ${\rm MP2Gate}=1$.

In sequence 4, when CLK and CLKB toggle from state 3, MN7 is blocked and MN8 conducts, causing MN3 to conduct due to MP2Ggate=1. As a result, ${\rm DB}=0$, and MP4 conducts, setting ${\rm D}=1$. With ${\rm MP2Gate}=1$, MN3 continues to conduct. Therefore, MN1 conducts while MN2 is blocked, resulting in state 4 with ${\rm MP1Gate}=0$ and ${\rm MP2Gate}=1$.

Additionally, if CLK remains in a low voltage state for a long time, the logic state will collapse due to leakage current.

The circuit works as a divide-by-2 divider circuit when the DC supply voltage is less than 1.6 V.

Six divide-by-2 divider-unit circuits are connected in cascade to realize a divide-by-64 divider as shown in Fig. 3. To obtain a differential input signal in the first unit divider, an inverting buffer used as a balun is added to the input stage.

The divider circuit is designed based on a 65nm CMOS process without using an inductor, resulting in a compact core area of 64 $\mu$m by 13 $\mu$m. The overall area including the pads is 200 $\mu$m by 240 $\mu$m, as shown in Fig. 4.

The oscilloscope output of the frequency divider circuit operating in digital logic mode was presented in Fig. 5 for a low VDD condition. The experimental conditions are summarized in Table 1. The digital logic signals measured for input frequencies ranging from 1 MHz to 1000 MHz are shown. In Fig. 5(d), as the input signal frequency exceeds the oscilloscope's measurement range, only the output signal is displayed. As the input signal frequency increases, the divider shows a tendency to require higher power consumption. When the VDD surpasses a certain threshold, the frequency divider stops operating in digital logic mode and transitions to operation as an Injection-Locked Frequency Divider (ILFD).

Considering the feedback of the output `D' and `DB' of the circuit in Fig. 1, each circuit connected to MN1-MN3-MN5 and MN2-MN4-MN6 has a structure in which an odd number of inverters are repeated. As a result, a ring oscillator structure connected to three inverters is formed separately, as shown in Fig. 6.

The logic threshold voltage VLT of the CMOS inverter circuit is expressed as ^[7]

,

where $V_{TN}$ is the threshold voltage of the NMOS, $V_{TP}$ is the threshold voltage of the PMOS, and $\beta_{N}$ and $\beta_{P}$ are the gain coefficients of the NMOS and PMOS, respectively. $\beta_{N}$ and $\beta_{P}$ are defined in terms of mobilities and oxide capacitances for corresponding materials as follows:

In the inverter circuit, the propagation delay time $T_{PAVG}$ related to the power supply voltage $V_{DD}$ and load capacitor $C_{L}$ is given by

In practical applications, since $V_{DD}$ is much larger than $V_{LT}$, $V_{TN}$ and $V_{TP}$, $T_{PAVG}$ can be simplified to

As VDD increases, $T_{PAVG}$ at each stage decreases and the non-linear characteristics of the circuit increase, approaching the high-frequency oscillation condition. When the oscillation condition is satisfied, the feedback path in Fig. 5 operates as a ring oscillator and a divider circuit. It operates as an ILFD in which the frequency of the input signal is equal to the harmonics or subharmonics of the oscillation frequency ^[5,6,9].

A large bias voltage increases the voltage swing at the drain and enhances the circuit nonlinearities ^[8]. The DC supply voltage is divided by the 2-cascode connected MOSFETs of the inserted inverter, which facilitates the generation of harmonic power as the DC supply voltage increases because the other circuits operating on the same power supply are 3-cascode connected.

As the DC supply voltage increases, a ring oscillator is formed through the feedback path such that the output oscillates at a frequency that satisfies the Barkhausen oscillation condition.

From (5), the oscillation frequency can be simply approximated as follows and is consequently linearly proportional to the supply voltage VDD

The fabricated die was tested for its RF characteristics on a 50 ohm-based printed board test fixture with 0.8 mil gold ball bonds. When the DC supply voltage is less than 1.6 V, the complete circuit operates as a divide-by-64 divider exactly obeying sequential digital logics up to 9 GHz. When the DC supply voltage is low, there is a negligible tiny output power in the absence of any input signal. As the voltage approaches 2 V, the circuit enters a state of multi-frequency self-oscillation. At this time, when a large signal is applied at the input, a series of large harmonic powers are generated by the balanced mixer composed of the differential pairs MN1-MN2 and MN3-MN4 ^[9] and the nonlinearity-enhanced inverters MN5-MP5 and MN6-MP6 ^[7].

In each unit oscillator circuit, the oscillation frequency is inversely proportional to the load resistance and capacitance of the output stage, such that the locking frequency of the oscillator circuit changes as the DC supply voltage changes. As the DC supply voltage increases, a mixed state occurs in which the oscillation characteristics, digital sequential logic division characteristics, and nonlinear harmonic generating characteristics of each unit divider circuit with different impedances interact with each other. As a result, the frequency range of operation as an ILFD is distributed over a series of discontinuous frequency bands with different division ratios.

Table 2 lists the characteristics of the ILFD measured between 2.4 GHz and 27.1 GHz. As the DC supply voltage changes, the ILFD operates in a frequency bandwidth smaller than 2.088 GHz around 2.4 GHz, 4.4 GHz, 6.2 GHz, 12.6 GHz, 19.1 GHz, 21.6 GHz, 24.7 GHz, and 27.1 GHz. Each band has a unique frequency division ratio ranging from 48 to 528 depending on the supply voltage as shown in Figs. 7 and 8.

Fig. 9 shows the output waveform measured in the ILFD mode featuring a 528-division ratio for an input signal of 27.1128 GHz and 3.15 dBm. Inset Fig. 9(a) shows the very sharp jitter characteristics measured in a narrow span of 10 kHz. In Fig. 9(b), the phase noise is -102.23 dBc at 100 kHz offset in its resolution bandwidth. The difference between the fundamental and the second harmonic is measured to be -5.83 dBc.

Table 3 compares the division ratio, the locking range, the power consumption, and the operating frequency with the figure of merits (FoM) ^[10] for previously reported CMOS dividers for higher than K-band. Other research teams have reported only on the ILFD characteristics with single frequency bands generated from single-stage circuits. However, the present paper, which features a multi-stage architecture, reports on the measurement and characterization of multiple frequency bands. In doing so, this paper demonstrates the existence of a unique synergetic operation between the multi-stage ILFD and divider circuits inducing this multiple frequency-band operation.

The designed circuit exhibits remarkable 528 and 384 division ratios at 27.1 GHz and 24.7 GHz respectively, which to the best of our knowledge are the highest ILFD division ratios reported in the literature, and which together with its low power consumption, results in FoMs of 7.4 and 1114, respectively. The circuit does not require a large internal inductor, resulting in a small die area of 0.048 mm${}^{2}$ including pads and a compact 830 um${}^{2}$ excluding them, which is promising for realizing an efficient integration with other circuits.

III. CONCLUSION

In this paper, a 65 nm CMOS-based 6-stage divider circuit is presented that performs exact-digital 64 division when the power supply voltage is low and operates as a multi-band ILFD up to 27.1 GHz when the supply voltage is high. This paper reports the novel phenomena of multi-band division with a unique division ratio depending on the bias voltage used with the multi-stage circuits. The ILFD has achieved a very high frequency division ratio up to 528 at 27.1 GHz, which is the highest ILFD division ratio reported to the best of our knowledge. With a low power consumption of 1.05 mW, the present circuit exhibits a high FoM of a 1114 with a 394-division ratio at 24.7 GHz in a very small area of 832 um2, making it a promising choice for efficient integration in communication circuits.