I. INTRODUCTION

In electronics, passive elements such as resistor, inductor, and capacitor are characterized as linear, time-invariant, and reciprocal. This reciprocity arises from their fabrication using conventional material that possess symmetric permittivity and permeability tensors. Traditionally, in wireless component design, the breaking of Lorentz reciprocity has been achieved by utilizing ferrite material with an external magnetic field bias, as seen in devices like isolators and circulators. However, ferrite-based devices are bulky and incompatible with CMOS IC fabrication, which limits their effectiveness. Additionally, the antenna interface for full-duplexing wireless communication system is crucial and can be realized through various means such as antenna pairs ^[1], shared antenna interfaces like the electrical balance duplexer ^[2] or circulator ^[3].

This study focuses on effectively integrating the circulator device into the CMOS system. Nonreciprocal passive circulators employing ferrite materials ^[4] have demonstrated excellent performance in terms of high linearity and low loss. However, they are not amenable to CMOS technology for integration. Furthermore, circulators that utilize the nonreciprocity of active transistors ^[3,5] suffer from high noise and poor linearity ^[6]. Nonlinear approaches have also been explored in optical communication systems ^[7], but they lead to a limited input power range and suffer from dynamic reciprocity ^[8]. Therefore, the need for a circulator with low noise, high linearity, and high isolation remains an ongoing challenge to researchers.

Linear periodically time-varying (LPTV) circuits have emerged as a solution to address the challenges of achieving magnet-less non-reciprocity. These circuits offer the potential for high performance, low cost, and compact size. Recent research has explored the development of magnetic-free non-reciprocal circulators based on staggered commutation with all-pass filter type ^[9] or N-path BPF type ^[10] networks.

In this work, we present a fully integrated circulator IC including not only multi-path staggered commutation networks but also artificial lumped-element transmission lines, which results in ultra-compact solution.

II. DESIGN AND ANALYSIS

To design a fully integrated circulator in CMOS technology, we used linear periodic time-variant (LPTV) property of band-pass filter (BPF) type gyrator in a staggered commutation network which was implemented in N-path switched capacitor array.

A. BPF type gyrator

Fig. 1 shows a two-port commutated N-path switched-capacitor network realized by using $N$ identical branches of a switch-capacitor-switch structure. The output switches are delayed with respect to the input set by $\Delta T > T_{s}/N$, where the value of $N$ is the number of the path and $T_{s}$ is the switching period. This network subjected to spatial-temporal modulation, can operate as a bandpass filter (BPF). The duration during which each switch is closed should be significantly shorter than the time constant of the shunt capacitor, $\tau \gg T_{s}/N$ ^[11]. Increasing N enhances the filter performance ^[12]. In this work, considering the circuit complexity and loss, the network was designed with four paths.

Fig. 2 shows a four-path two-port BPF-based gyrator using NMOS switches. The capacitance was chosen to satisfy the condition of the bandpass filtering characteristic, $C \gg 1/(2\pi\cdot f_{s}\cdot Z_{0})$, where $f_{s}$ is the operation frequency and $Z_{0}$ is the characteristic impedance of the system. The switches were driven by clocks having four phases with the duty cycle of 25%. Two clock sets (LO a$<1:4>$ and LO b$<1:4>$) had the phase shift of $90^\circ$. The switch design was optimized considering on-resistance and parasitic capacitance.

The complete $S$-parameter of the gyrator can be expressed as ^[6]

$ S(f_{{\rm S}})=\left[\begin{array}{cc} {{\rm sinc}^{2} \left(\frac{\pi }{4} \right)-1} & {{\rm sinc}^{2} \left(\frac{\pi }{4} \right){\rm e}^{\frac{{\rm -j\pi }}{2} } } \\ {{\rm sinc}^{2} \left(\frac{\pi }{4} \right){\rm e}^{\frac{{\rm +j\pi }}{2} } } & {{\rm sinc}^{2} \left(\frac{\pi }{4} \right)-1} \end{array}\!\!\right]. $

The $S$-parameter matrix reveals that the magnitudes of ${S}_{12} $and ${S}_{21}$ are reciprocal, but their phases are non-reciprocal. Fig. 3 shows magnitude and phase response with S-parameter simulations. In Fig. 3(a), the gyrator exhibits a bandpass filter characteristic with the insertion loss of 5 dB and return loss of -15 dB. Fig. 3(b) illustrates the approximate phase difference of $175^\circ$ between $S_{21}$ and $S_{12}$.

Fig. 1. Commutated multipath network.

Fig. 2. BPF type gyrator.

Fig. 3. Simulated results of S-parameters of gyrator.

B. Clock Signal Generator

To provide the required clock signals to the switches, a voltage-controlled oscillator (VCO) was designed for clock signal generation. Fig. 4 shows the circuit topology of the VCO. The VCO consists of a PMOS cross-coupled pair, a capacitor bank digitally controlled by three bits for coarse-tuning, and a varactor bank for analog fine-tuning. The PMOS cross-coupled pair was chosen for low phase-noise characteristic. The isolated bulk terminals and the low mobility of holes of PMOS devices result in inherently less thermal and flicker noise contribution than NMOS devices ^[13]. The VCO was designed with a supply voltage of 1.2 V and current consumption of 6 mA. The simulation results show the center frequency of 9.6 GHz, the phase noise of -106 dBc/Hz at the offset frequency of 100 kHz, and the tunning range of 590 MHz with controlled voltages from 0 to 1.2 V.

To design 2.4 GHz clock signals with the duty cycle of 25%, the conventional Johnson-counter-based dividers were employed as shown in Fig. 5. The divide-by-4 dividers were designed with high-speed D flip-flops. Because the clock signals were required to drive large NMOS switches in commutated paths, several buffers were placed right before the switches. To achieve staggered commutation operation for phase non-reciprocity, the delay of $90^\circ$ degree between LO a$<1:4>$ and LO b$<1:4>$ was designed by a digitally-controlled delay line (DCDL) for the coarse-tuning step, and then an analog varactor bank was utilized for fine-tuning. Fig. 6 shows the NAND-based telescopic 5-stage DCDL.

Fig. 4. Configuration of VCO.

Fig. 5. Configuration of divide-by-4 divider.

Fig. 6. Configuration of DCDL.

Table 1 summarizes the design parameters.

Table 1. Design parameter summary.

Block	Parameter	Value
BPF type Gyrator	Operating frequency	2.4 GHz
	W/L of NMOS switch	250 nm/30 nm
	Capacitor in N-path	16 pF
Artificial Transmission Line	Inductor	3 nH
	Capacitor	1.9 pF
Clock Generator	VCO center frequency	9.6 GHz
	VCO tunning range	590 MHz
	VCO phase noise at 1MHz offset	-105 dBc/Hz
	DCDL delay time	100 ps

III. IMPLEMENTATION AND MEASUREMENT

The circulator IC was implemented using Samsung 28 nm RF CMOS process. Fig. 7 shows the block diagram of the overall circulator. It consists of three subblocks: lumped-element transmission lines, a four-path two-port BPF type gyrator, and a clock signal generator. The size of the fully integrated transmission lines was miniatured by using high-pass filter type capacitor-inductor-capacitor (C-L-C) network with on-chip metal-insulator-metal (MIM) capacitor and spiral inductor. The inductor was implemented on the top metal layer of thick copper with the inductance of 3 nH. The capacitance was chosen to be 1.9 pF. In the gyrator, the width and length of the NMOS devices were 200 $\mu$m and 0.1 $\mu$m, respectively. The capacitance between the switches was designed to be 16 pF. Fig. 8 shows the microphotograph of the fabricated chip. The overall size is 970 $\mu$m $\times$ 960 $\mu$m excluding all the bonding pads.

Fig. 9 shows the measured S-parameters with simulation results. Simulations were conducted under not only typical condition (plotted by black and thick lines) but also variation of process, voltage, and temperature (PVT) including CMOS corners of slow, nominal, and fast conditions; supply voltage change by 10%; and temperature range from -$30^\circ$C to $80^\circ$C (plotted by gray and thin lines).

Fig. 7. Overall block diagram of the fully integrated circulator.

Fig. 8. Photograph of the circulator IC.

Fig. 9. Measured and simulated results of S-parameters of implemented circulator.

Fig. 10. Measured results of noise-figures of implemented circulator.

The measured circulator characteristics are shown in the narrowband near 2.4 GHz. Among three ports, in the frequency range of 2.39-2.4 GHz, the measured insertion losses are in the range of 4.5-5.5 dB (about 1-2 dB worse than the simulation), while the maximum isolation features are in the range of 35.7-44.8 dB (about 5-8 dB worse than the simulation). These discrepancies are primarily attributed to parasitic components in the devices which could not predict in the simulation because of the device modeling limitation. The large signal performance was measured at the frequency of 2.4 GHz among three ports. IP1dBs were 18.2 dBm (port1-port2), 18.5 dBm (port2-port3), and 16.3 dBm (port1-port3). The measured minimum noise-figures were 6.1 dB (port1-port2), 5.8 dB (port2-port3), and 9.8 dB (port1-port3) within the frequency range of 2.39-2.4 GHz as shown in Fig. 10. The performance between port1 and port3 is the worst because the gyrator circuit is located in the path. The circulator IC consumes 7.2 mW for the VCO block and 14.4 mW for the dividers and DCDL block.

Table 2 compares our proposed circulator IC with other designs reported in the literature. Compared to the circulators employing staggered commutation through filters ^[9,10], integration condition should be considered. The circulator in ^[9], which relies on external clock signals, shows worse maximum isolation performance by 17.7-35.3 dB than this work. Similarly for the circulator in ^[10], which used not only external clock signals but also off-chip components to implement transmission lines, the circulator in this work shows lower power consumption by 69%. When this work is compared with fully integrated circulators ^[14,15], the presented circulator shows better characteristics than the active quasi-circulator ^[14] in terms of insertion loss, isolation, power dissipation, and size. Even if the integrated transmission lines on the insulator substrate in ^[15] resulted in slightly better insertion loss by 1.5-2.4 dB, the chip size and power dissipation were significantly larger than our design.

IV. CONCLUSION

In this work, we have presented the fully integrated non-magnetic CMOS circulator IC based on a four-path BPF type staggered commutation network. Even if it provides slightly large loss because of full integration including lumped-element transmission lines, it shows good isolation performance among ports as well as an ultra-compact size.