SongDongsup1
-
(College of AI Convergence Electronic Engineering, Hoseo university, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Test access mechanism, IEEE 1500, AI semiconductor, Tile-based design, mirrored core layout
I. INTRODUCTION
Since the historic match in 2016 between Lee Sedol, one of the world's best Go players,
and AlphaGo, Artificial Intelligence (AI) has become widely used across various fields,
including home appliances, smart devices, the internet, and autonomous driving. As
AI technology expands across industries, one key area that requires significant advancements
is "AI semiconductors." Recently, not only traditional semiconductor leaders but also
global big-tech companies have been accelerating AI semiconductor development by making
massive investments and pursuing mergers and acquisitions.
An AI semiconductor is a specialized processor designed to efficiently process vast
amounts of training data within a short period of time. Unlike traditional CPUs, which
process data sequentially, AI semiconductors rely on a hardware architecture optimized
for parallel data processing to achieve high-speed, large-scale computations. The
demand for parallel data processing had led to the integration of tens or hundreds
of identical Neural Processing Unit (NPU) cores within a single chip, representing
a distinctive characteristic of AI semiconductor architecture. This architectural
shift has introduced significant changes in semiconductor design, known as a tile-based
design methodology. The tile-based design methodology arranges design blocks in adjacent
tile structures so that signal connections occur at tile boundaries through physical
signal contacts, rather than using routing resources on the chip's top-level are and
this approach enables a reduction in chip area [1, 2].
AI semiconductors are extensively used in industries requiring high reliability, such
as high-cost data servers, automotive semiconductors for autonomous driving, and medical
semiconductors. Consequently, the development of advanced Design for Testability (DFT)
methodologies to ensure high-reliability of AI semiconductor has become increasingly
critical. In traditional System on Chip (SOC) design, a bottom-up DFT design approach
is commonly adopted. This approach involves integrating DFT feature- such as scan
chains, Built-In Self-Test (BIST), and wrapper circuits-within individual cores or
blocks that include logic circuits, embedded memories, and IP components. These core-level
DFT circuits are subsequently integrated at the system chip using test standards like
IEEE 1500 or IEEE 1687 to provide adequate test access [3, 4]. However, conventional IEEE 1500 or IEEE 1687 standards typically requires significant
routing resources at the chip's top-level to connect the Test Top Controller to the
core-level DFT circuits. This traditional bottom-up DFT architecture is increasingly
incompatible with the tile-based design methodology which is widely employed in modern
AI semiconductor architecture [5-8]. This paper presents a novel design methodology
for providing effective test access to tile-level DFT circuits in AI semiconductors.
Instead of consuming routing resources in the chip's top-level area, the proposed
approach enables the application of the IEEE 1500 test standard to tile-based AI semiconductors
by utilizing pass-through wiring of adjacent core blocks.
To enhance the efficiency of inter-tile signal connections, tile-based designs often
employ a design methodology where the tile layout is mirrored and reused symmetrically
along vertical or horizontal axes. However, this mirroring reverses signal direction,
making it impossible to provide test access through pass-through wiring between adjacent
blocks. To resolve this issue, the proposed pass-through wiring design supports bidirectional
signals, with the signal direction determined by the placement of tiles within the
chip. This enables the reuse of mirrored tile layouts in tile-based AI semiconductor
without the need of redesign core blocks.
With recent advancement in 2.5D-IC and 3D-IC package technologies, the positions of
tiles in AI semiconductors are frequently adjusted to accommodate the configuration
changes of chiplets. Redesigning pass-through test access for each tile to adapt to
these changes is not only time-consuming but also significantly increases design costs.
The proposed test access design methodology enables the reuse of tile designs without
modification, even when tile position is changed due to rearrangements in AI semiconductors.
II. TEST ACCESS STANDARDS AND TILE-BASED SEMICONDUCTOR DESIGN
1. Bottom-up DFT design methodology and IEEE 1500 test access signal connection
The IEEE 1500 standard defines the structure and mechanisms for testing embedded cores
of a system chip with the objectives of enhancing portability and reusability of embedded
cores, reducing test complexity, minimizing test costs, and improving test reliability.
The IEEE 1500 standard specifies the Wrapper Serial Port (WSP) and Wrapper Parallel
Port (WPP), enabling independent testing of cores or integrated testing with other
parts of the system chip through a wrapper that surrounds each embedded core [3, 5]. The wrapper serial port is a mandatory component defined by IEEE 1500. The wrapper
serial port is fully compatible with the IEEE 1149.1 test controller and is used to
provide serial test access to DFT circuits within the core blocks [9, 10]. By providing appropriate access to the test circuits within a system chip, the IEEE
1500 test access standard is widely used to facilitate efficient testing for both
system chip designers and test engineers.
Fig. 1 illustrates an example of a core block where the IEEE 1500 standard has been applied
to a system chip. The wrapper serial port is used to program and output data from
the wrapper instruction register (WIR) and data registers, and it includes the wrapper
serial input (WSI) and wrapper serial output (WSO) ports, as well as the wrapper serial
control (WSC) port. The WSC port controls the operation of IEEE 1500 registers and
consists of signals such as WRCK, WRSTN, ShiftWR, UpdateWR, CaptureWR, and SelectWIR.
The IEEE 1500 standard effectively provides appropriate test access to the DFT circuits
within core blocks, for example, SRAM BIST for embedded memory or SCAN codec for scan
compression, through data registers like the wrapper control data register (WCDR)
and wrapper data register (WDR). Specifically, the {WCDR} is a register used to send
commands such as reset, test initiation, and state register reading to test circuits
within the core, while the WDR serves as a register to output test results externally.
The IEEE 1500 standard is based on a bottom-up design methodology for SoC architecture.
It assumes the use of routing resources in the chip's top-level area to connect signals
from the test top controller, located in either the chip's top area or a designated
base core block, to the wrapper serial ports of each core block. Fig. 2 illustrates the connection between four embedded core blocks with IEEE 1500 wrapper
serial ports and the IEEE 1149.1-based test top controller located in the base core
block. Since the wrapper serial port consists of a wrapper serial input, a wrapper
serial output, and six wrapper serial control port signals, a total of eight signal
connections are required between the base core block and each core block. These connections
utilize routing resources in the chip's top-level area. However, in tile-based system
chip design, which has become the mainstream architecture for AI semiconductors, the
design methodology does not permit the use of top-level routing resources between
core blocks. Consequently, an enhanced design methodology is required to provide test
access to each core block using the IEEE 1500 standard in a tile-based AI semiconductor
design.
Fig. 1. A system chip with IEEE 1500 test access.
Fig. 2. Traditional signal connection between test top controller and WSP.
2. Tile-based design methodology and IEEE 1500 test access signal
AI semiconductors incorporate tens or even hundreds of NPU core blocks to achieve
high-speed computation. These core blocks are typically identical in design, enabling
layout reuse to enhance efficiency. This approach leverages a tile-based semiconductor
design methodology, which simplifies the design process, reduces power consumption,
and minimizes chip area. A tile refers to an individual block within a SoC that integrates
both logic and embedded memory. By arranging tiles in direct adjacency, the tile-based
design methodology facilitates inter-tile connections without relying on top-level
routing resources. This physical proximity allows signal connections to be established
through direct contact between tiles, as described in [1, 2].
In tile-based design, the physical contact between tiles eliminates the availability
of routing resources in the chip's top-level area. This poses significant challenges
for integrating traditional IEEE test access mechanisms into tile-based designs, as
the conventional IEEE 1500 test access approach connects the test top controller to
the wrapper serial port by utilizing top-level routing resources. To address these
challenges, [11, 12] introduced test access from the test top controller to DFT circuits within core blocks
by implementing pass-through wiring. Pass-through wiring consists of routing paths
within a tile that transmit signals across the tile to other regions of the chip,
thereby simplifying the layout and reducing chip area. However, the method proposed
in [11, 12] is restricted to test circuits compliant with the IEEE 1687 standard and cannot be
applied to tiles requiring IEEE 1500 access. Furthermore, the proposed method is incompatible
with tile design methodologies that rely on mirrored layouts.
In tile-based designs, Network-on-Chip (NoC) architectures are widely adopted due
to significant advantages in scalability, bandwidth, and performance compared to traditional
bus-based structures or point-to-point connections. NoC topology refers to the network
structure that facilitates efficient data communication comprising multiple processor
cores. Various NoC topologies, such as crossbar, star, ring, tree, 2D mesh, 3D cube,
and 4D hypercube, are utilized depending on performance and efficiency requirements.
Among these, the 2D mesh topology is the most commonly employed in system chip designs
due to its simplicity in implementation and scalability [13, 14].
Fig. 3 illustrates a tile-based design utilizing a 2D mesh NoC topology. In the design,
physical arrangement of tile-based core blocks often involves a layout mirroring methodology,
which includes rotating or flipping specific core block layouts along horizontal or
vertical axes. This approach optimizes critical metrics such as chip area, connectivity,
system performance, power consumption, and signal delay. While a layout mirroring
methodology in a 2D mesh NoC topology enhances signal transmission between adjacent
tiles, it introduces challenges in accessing test signals via pass-through wiring.
Fig. 4 highlights this issue, where the directional properties of IEEE 1500 wrapper serial
port signals lead to conflicts in signal direction between adjacent tiles. To address
this limitation, Chapter 3 proposes a novel pass-through wiring design methodology
to effectively resolve these signal direction conflicts and enhance test access in
tile-based designs with layout mirroring
Fig. 3. Tile-based core blocks with 2D mesh NOC topology.
Fig. 4. Conflict of test access signal at the border of tiles due to mirrored layout.
III. ADVANCED IEEE 1500 COMPLIANT TEST ACCESS MECHANISM DESIGN
This chapter describes a test access mechanism that can be effectively applied to
tile-based designs where core block layouts are mirrored along horizontal or vertical
axes. The position of the test top controller on the system chip is closely related
to the implementation of pass-through wiring for test access signals. If the test
top controller is located at the top or bottom of the system chip, the pass-through
wiring for test access needs to consider only vertical routing, either from the top
to the bottom or vice versa. However, if the test top controller is positioned on
the left or right side of the chip, the pass-through wiring must consider horizontal
routing, from left to right or right to left. This chapter explains the case where
the test top controller is located at the bottom of the system chip, requiring vertical
pass-through wiring. The proposed test access mechanism can be applied without modification
when the test top controller is placed on the left or right side of the system chip.
1. Test Access Mechanism for IEEE 1500 Wrapper Serial Control Signals
Fig. 5(a) presents a novel test access mechanism designed to provide IEEE 1500 wrapper serial
control signals within a tile-based architecture, where the core block layout is vertically
mirrored and reused. In this design, WSC_PRI represents the primary port of the pass-through
wiring, comprising signals such as WRCK_PRI, WRSTN_PRI, ShiftWR_PRI, UpdateWR_PRI,
CaptureWR_PRI, and SelectWIR_PRI. Similarly, WSC_SEC denotes the secondary port, including
WRCK_SEC, WRSTN_SEC, ShiftWR_SEC, UpdateWR_SEC, CaptureWR_SEC, and SelectWIR_SEC.
Both WSC_PRI and WSC_SEC are implemented as bidirectional ports with high-impedance
output drivers to ensure stable operation, even when external input signals are set
to logic 1 or 0. The signal direction for WSC_PRI and WSC_SEC is controlled by the
UP_DOWN signal, which is set to logic 1 or 0 based on the tile's position and the
use of layout mirroring. This signal can be connected to VDD or VSS via tie cells
on the system chip, eliminating the need for additional space or routing resources
between core blocks.
Fig. 5(b) shows the flow of wrapper serial control signals, highlighted by thick red lines,
in a tile where the UP_DOWN signal is fixed at 1 during system chip configuration.
In this configuration, WSC_PRI functions as an input port, while WSC_SEC serves as
an output port, creating a pass-through connection from WSC_PRI to WSC_SEC. Simultaneously,
the wrapper serial control signals are delivered to the wrapper serial port within
the tile.
Similarly, Fig. 5(c) illustrates the flow of wrapper serial control signals in a tile with the UP_DOWN
signal fixed at 0. In this case, WSC_PRI operates as an output port, and WSC_SEC functions
as an input port, forming a pass-through connection from WSC_SEC to WSC_PRI. To ensure
signal stability, two AND gates, SEC_AND and PRI_AND, are employed to set the unused
direction's signals to 0, based on the UP_DOWN signal. This mechanism disables the
unused input of the WSI_OR gate, ensuring reliable delivery of wrapper serial control
signals to the wrapper serial port.
Fig. 5. Proposed bidirectional wiring for IEEE 1500 wrapper serial control signals
in mirrored tile layouts.
2. Test Access Mechanism for IEEE 1500 Wrapper Serial Input and Output signals
WSI and WSO of the IEEE 1500 standard operate as serial data input and output, respectively.
Fig. 6(a) presents a new test access mechanism for enabling test access via WSI and WSO in
a tile-based design with vertically mirrored and reused core block layouts. WSIO_PRI
and WSIO_SEC can operate as either WSI or WSO, depending on the tile's layout mirroring,
with their roles determined by the UP_DOWN signal.
For tiles where the UP_DOWN signal is fixed at 1 as shown in Fig. 6(b), WSIO_PRI functions as the WSI, connecting to the WSI of the wrapper serial port
within the tile. Concurrently, WSIO_SEC serves as the WSO, connecting to the WSO of
the wrapper serial port. Conversely, in tiles where the UP_DOWN signal is fixed at
0 as shown in Fig. 6(c), WSIO_PRI functions as the WSO, connecting to the WSO of the wrapper serial port,
while WSIO_SEC operates as the WSI, connecting to the WSI.
Similar to the wrapper serial control signals, WSIO_PRI and WSIO_SEC are configured
as bidirectional ports to ensure stable operation even when their output drivers are
in high-impedance mode. Unlike the wrapper serial control signals, serial data requires
not only a path to deliver test instructions or test data to each tile but also a
loopback path to return test responses from each tile back to the top-level test controller.
This is to enable the test top controller to analyze the test response results or
to output the test responses externally for detailed analysis. WSIO_PT_PRI and WSIO_PT_SEC
provide pass-through wiring to return loopback serial data signals to the test top
controller. The complete connections within the system chip are illustrated in Fig. 7.
Fig. 6. Test access mechanism for IEEE 1500 wrapper serial input and output signals
with mirrored tile layouts.
Fig. 7. Configuration of an AI semiconductor with a 3?2 mirrored tile matrix and IEEE
1500-compliant test access.
3. Configuration of AI semiconductor with improved test access mechanism
Fig. 7 illustrates an example configuration of an AI semiconductor designed with a tile-based
methodology, including a base core block with a test top controller and six core blocks
whose layouts are horizontally and vertically mirrored and reused. The six core blocks
are arranged in a $3 \times 2$ matrix and named following the naming convention BLK_R$\{$row$\}$C$\{$column$\}$,
resulting in BLK_R1C1, BLK_R2C1, BLK_R3C1, BLK_R1C2, BLK_R2C2, and BLK_R3C2. Note
that the UP_DOWN signal is fixed at 1 or 0 according to the placement of each tile
within the system chip. In tile-based designs with mirrored layouts, conventional
pass-through wiring cannot make a path from the chip's bottom to the top due to directional
conflicts at tile boundaries. To resolve this, the proposed test access mechanism
is designed as a bidirectional bus, with its direction is determined by whether the
UP_DOWN signal is set to 1 or 0.
In this example, the UP_DOWN signal is fixed at 1 for the two tiles in the first row
(BLK_R1C1, BLK_R1C2). For the two tiles in the second row (BLK_R2C1, BLK_R2C2), the
UP_DOWN signal is set to 0 to maintain the IEEE 1500 pass-through wiring direction
from the bottom to the top of the chip. Similarly, the tiles in the third row (BLK_R3C1,
BLK_R3C2) have the UP_DOWN signal set to 1, consistent with the pass-through signal
direction of the first row. The WSIO_LOOPBACK signal, located outside the tiles, provides
a loopback path that returns the serial data to the test top controller located at
the bottom of the chip. In Fig. 7, signals marked in thick red lines indicate the active test access paths as determined
by each tile's UP_DOWN signal connection.
Wrapper serial control signals from the test top controller are directly delivered
to the tiles in the first row (BLK_R1C1 and BLK_R1C2) through physical connections,
eliminating the need for top-level routing resources. Within these tiles, the signals
are routed to the wrapper serial port and simultaneously passed to the adjacent tiles
in the second row (BLK_R2C1 and BLK_R2C2) via pass-through wiring. Despite the vertical
mirroring of the second-row tile layouts relative to the first row, the wrapper serial
control signals are effectively propagated to the third-row tiles (BLK_R3C1 and BLK_R3C2)
by configuring the directional pass-through paths appropriately.
This mechanism ensures reliable delivery of wrapper serial control signals from the
test top controller to the wrapper serial ports of all tiles across the system chip.
Similarly, wrapper serial input and output signals are transmitted from the test top
controller to the topmost tiles and subsequently looped back to the test top controller
via WSIO_LOOPBACK connections and internal tile pass-through wiring.
As shown in Fig. 7, the proposed test access mechanism requires additional hardware components compared
to the standard IEEE 11500 implementation. Specially, it includes two 2-input NAND
gates, six bi-directional buffers, two inverters, two 2:1 multiplexers, and one OR
gates. When measured in terms of unit gate count using a 2-input NAND gate as the
reference, the additional hardware amounts to approximately $50{\sim} 60$ gate counts.
Thus, the hardware overhead introduced by the new test mechanism is negligible.
Fig. 8. Signal timing diagram for proposed test access mechanism.
IV. PERFORMANCE ANALYSIS OF THE PROPOSED TEST ACCESS MECHANISM
The proposed test access mechanism is implemented using Verilog HDL and verified through
simulation. Fig.~8 illustrates the IEEE 1500 signal timing for the base core block
and two tile-based blocks to explain the performance of the proposed methodology.
In this figure, ${\{}$Signal${\}}$_tile# denotes the IEEE 1500 pass-through wiring
signals for each tile, representing the path from $\mathrm{\{}$Signal$\mathrm{\}}$_PRI
to $\mathrm{\{}$Signal$\mathrm{\}}$_SEC, or vice versa, depending on whether the UP_DOWN
signal is fixed at 0 or 1. Tile1 refers to the tile in the first row adjacent to the
base core block, while Tile2 represents the tile in the second row. The $\mathrm{\{}$Signal$\mathrm{\}}$
includes wrapper serial control signals such as WRCK, SelectWIR, CaptureWR, ShiftWR,
and UpdateWR. The WSI_tile# and WSO_tile# signals define the wrapper serial data path,
indicating the route from WSIO_PRI (or WSIO_SEC) to the wrapper serial port, and from
the wrapper serial port to WSIO_SEC (or WSIO_PRI), based on the tile's mirroring configuration.
Additionally, the WSIO_PT_tile# signal represents the loopback path for serial test
data within each tile block, connecting WSIO_PT_PRI and WSIO_PT_SEC. This path operates
from WSIO_PT_PRI to WSIO_PT_SEC, or vice versa, depending on the tile's mirroring
state. The gray-shaded regions in the timing diagram indicate signal skew between
the base core block and each respective tile.
The test access mechanism of the proposed IEEE 1500 network is based on source-synchronous
timing, which delivers IEEE 1500 signals along with the WRCK clock. Note that the
skew of all signals, except WSI_tile# and WSO_tile#, accumulates with the skew introduced
in the previous tile. For instance, the skew of the SelectWIR_tile2 signal in tile2
represents the combined skew from tile1 and the skew generated within tile2 itself.
In contrast, WSI_tile# and WSO_tile# signals, which are consumed or output at the
wrapper serial port within each tile, do not accumulate skew across tiles. Instead,
their skew only reflects the timing offset between adjacent tiles.
Ensuring that test access signals generated from the base core block operate with
precise timing in each tile is critical for large-scale chips, such as AI semiconductors.
When testing AI semiconductors using IEEE 1500 protocols, the Capture, Shift, and
Update operations must be repeatedly applied. To ensure accurate timing for the Capture
and Update operations in the proposed test access mechanism across all tiles, the
condition specified in Equation (1) must be satisfied.
Here, WRCK_period refers to the clock period of the WRCK signal used during testing,
MAX_skew represents the maximum skew observed for the CaptureWR_tile#, ShiftWR_tile#,
and UpdateWR_tile# signals within each tile, and Number_of_Stack indicates the number
of stackable tile rows. As described in Equation (1), the skew of the CaptureWR_tile#, ShiftWR_tile#, and UpdateWR_tile# signals traversing
the tiles is inversely proportional to the number of stackable tile rows. Therefore,
minimizing the skew among IEEE 1500 signals passing through each tile enables an increased
number of tile blocks to be arranged in rows.
The proposed test access mechanism utilized pass-through wiring within tiles, enabling
signal routing to be optimized for minimizing MAX_skew by maintaining uniformity in
the wiring of these signals. If MAX_skew exceeds the allowable limit relative to the
implemented Number_of_Stack, WRCK_period can be adjusted during testing to satisfy
the requirements of Equation (1). The test time associated with the Capture and Update operations in the IEEE 1500-based
testing framework is significantly smaller compared to the Shift operation. As a result,
reducing the WRCK_period has a negligible impact on the overall testing process in
terms of test time.
To perform the IEEE 1500 standard shift operation with correct timing, the condition
in Equation (2) must be satisfied.
Here, max_prop(WSI_tile#) and max_prop(WSO_tile#) represent the maximum signal delay
for the WSI_tile# and WSO_tile# signals across all tiles respectively. Additionally,
$\sum prop(WSIO\_PT\_tile\#)$ represents the total propagation delay for the WSIO_PT_tile#
signal for all tiles.
Eq. (2) specifies that the propagation delay of serial test data must not exceed half of
the WRCK period. To secure a half-cycle hold margin relative to the WRCK clock, serial
test data are typically applied on the falling edge of the WRCK clock, while the actual
data update during the shift operation occurs on the rising edge. The register-to-register
propagation path of serial test data comprises three distinct paths: the WSI_tile#
path within each tile, the WSO_tile# path within each tile, and the WSIO_PT_tile#
path across all tiles. The maximum propagation delay for each of these three serial
test data paths must not exceed $\frac{WRCK_period}{2}$.
Among the three propagation delay components in Eq. (2), $\sum prop(WSIO\_PT\_tile\#)$ which is the cumulative propagation delay of the WSIO_PT_tile#
path is significantly larger than that of components max_prop(WSI_tile#) or max_prop(WSO_tile#).
Therefore, maintaining a small $\sum prop(WSIO\_PT\_tile\#)$ value is essential for
increasing the WRCK frequency during the shift operation. Furthermore, since the shift
operation constitutes the majority of IEEE 1500 testing process, designing with minimal
$\sum prop(WSIO\_PT\_tile\#)$ value is crucial for reducing the overall test time.
Fig. 9 illustrates a test access mechanism in which pipeline registers are inserted into
each tile to minimize the cumulative propagation delay, $\sum prop(WSIO\_PT\_tile\#)$.
While inserting pipelines into the wrapper serial control signal paths to increase
the operating frequency of WRCK is not feasible due to incompatibility with the IEEE
1149.1 protocol, pipeline insertion is feasible for the serial test data paths of
the wrapper serial input and wrapper serial output, as these paths maintain compliant
with the IEEE 1149.1 protocol. By employing the pipelined test access mechanism, Eq.
(2) can be modified to Eq. (3), facilitating an increase in the WRCK operating frequency during the shift operation,
thereby reducing overall test time.
While the proposed test access mechanism demonstrates promising results, real-world
implementation may present additional challenges. Signal integrity issues, such as
crosstalk and electromagnetic interference, could impact the reliability of bidirectional
pass-through wiring, particularly in densely packed tile-based designs. Additionally,
manufacturing constraints including process variations may affect the uniformity of
inter-tile connections, potentially leading to timing mismatches.
Fig. 9. Test access mechanism with pipelines to reduce test time.
V. CONCLUSIONS
Tile-based design methodology with vertically or horizontally mirrored core block
layouts has become a dominant approach in the design of AI semiconductors. This paper
presents a novel design methodology to provide effective IEEE 1500 standard-based
test access for individual tiles in AI semiconductors. The proposed approach leverages
pass-through wiring within tiles, enabling test access to all tiles without utilizing
the chip's top-level routing resources. To ensure stable test access in designs with
vertically or horizontally mirrored layouts, the pass-through paths are implemented
as bidirectional signals, effectively preventing signal conflicts at tile boundaries.
An equation is derived based on the proposed test access mechanism to establish the
relationship between the number of tile rows that can be integrated and the operating
frequency. Additionally, a pipelined test access methodology is introduced to reduce
test time by increasing the frequency of the shift operation. While this paper focuses
on AI semiconductors with vertically mirrored core block layouts for clarity, the
proposed test access mechanism can be directly applied to horizontally mirrored designs
without modification.
ACKNOWLEDGMENTS
This research was supported by the Academic Research Fund of Hoseo University
in 2024 (2024-0145-01).
References
Y. Dong G. Giles, G. L. Li, J. Rearick, J. Schulze, and J. Wingfield, ``Maximizing
scan pin and bandwidth utilization with a scan routing fabric,'' Proc. of IEEE International
Test Conference, pp. 1-10, 2017.
A. Sehgal, J. Fitzgerald, and J. Rearick, `` Test cost reduction for the AMDTM Athlon
processor using test partitioning,'' Proc. of IEEE International Test Conference,
pp. 1-10, 2007.
``IEEE Standard Testability Method for Embeded Core-based Integrated Circuits,'' IEEE
Std 1500-2022 (Rivision of IEEE Std 1500-2005), pp. 1-168, 2022.
``IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor
Device,'' IEEE Std 1687-2014, pp. 1–283, 2014.
E. J. Marinissen and Y. Zorian, ``IEEE Std 1500 enables modular SoC testing,'' IEEE
Design & Test of Computers, vol. 26, no. 1, pp. 8-17, 2009.
K.-J. Lee, T.-Y. Hsieh, C.-Y. Chang, Y.-T. Hong, and W.-C. Huang, ``On-chip SOC test
platform design based on IEEE 1500 standard,'' IEEE Transactions on Very Large Scale
Integration Systems, vol. 18, no. 7, pp. 1134-1149, 2010.
Z. Zhong, G. Li, Q. Yang, and K. Chakrabarty, ``Access-time minimization for the IJTAG
network using data broadcast and hardware parallelism,'' IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 40, no. 1, pp. 185-198, 2021.
F. G. Zadegan, Z. Zhang, K. Petersén, and E. Larsson, ``Reusing IEEE 1687-compatible
instruments and sub-network over a system bus,'' Proc. of IEEE International Test
Conference, pp. 219-228, 2022.
P. Bernardi, M. Rebaudengo, M. S. Reorda, and M. Violante, ``A P1500-compatible programmable
BIST approach for the test of embedded flash memories,'' Proc. of Design, Automation
and Test in Europe Conference and Exhibition, pp. 720-725, 2003.
``IEEE Standard for Test Access Port and Boundary-Scan Architecture,'' IEEE Std 1149.1-2013(Revision
of IEEE Std 1149.1-2001), pp. 1-444, 2013.
V. Yellapragada, S. Raman, B. Shivaray, L. Romain, B. NadeauDostie, and M. Keim, ``Implementing
design-for-test within a tile-based design methodology - Challenges and solutions,''
Proc. of IEEE International Test Conference in Asia, pp. 43-48, 2018
J. F. Côté, M Kassab, W. Janiszewski, R. Rodrigues,
R. Meier, and B. Kaczmarek, ``Streaming scan network (SSN): An efficient packetized
data Nnetwork for testing of complex SoCs,'' Proc. of IEEE International Test Conference,
pp. 1-10, 2020
A. Q. Ansari, M. R. Ansari, and M. A. Khan, ``Performance evaluation of various parameters
of network-on-chip (NoC) for different topologies,'' Proc. of Annual IEEE India Conference,
pp. 1-4, 2015
A. Kamath, G. Saxena, and B. Talawar, ``Analysis of ring topology for NoC architecture,''
Proc. of International Conference on Computing and Network Communications, pp. 381-388,
2015
Dongsup Song received his B.S. degree from the Department of Electrical Engineering,
Konkuk University, Seoul, Korea, in 2000, his M.S. and Ph.D. degrees in electrical
and electronics engineering, Yonsei University, Seoul, Korea, in 2002 and 2007, respectively.
He was a Principal DFT engineer with Samsung Electronics, Korea, from 2007 to 2021
and a Senior Staff Engineer in the EDA Group of Synopsys Korea from 2021 to 2024.
In 2024, he joined the Faculty of Electronic Engineering, Hoseo University, ChungNam,
Korea, where he is currently Professor. His research interests include AI driven DFT,
3D-IC DFT, DFT for automotive, and high quality DFT.