Keeth B., Baker R.J., Johnson B., Lin F., 2007, DRAM Circuit Design: Fundamental and High-Speed Topics 2nd ed., Wiley-IEEE Press

Jacob B., Ng S.W, Wang D.T., 2007, Memory Systems: Cache, DRAM, Disk, 1st ed., Morgan Kaufmann

Kim C., Lee H.-W., Song J., 2016, Memory Interfaces: Past, Present, and Future, IEEE Solid-State Circuits Magazine, Vol. 8, No. 2, pp. 23-34

Vollrath J., Schwizer J., Gnat M., Schneider R., Johnson B., 2006, DDR2 DRAM output timing optimization, 2006 IEEE International Workshop on Memory Technology, Design, and Testing (MTDT’06), Vol. design, No. and testing (mtdt’06), pp. 49-54

Lingambudi A., Vijay S., Becker W.D., Raghavendra P., Sethuraman S., Pullelli S., 2016, Improve timing margins on multi-rank DDR3 RDIMM using read-on die termination sequencing, 2016 IEEE Annual India Conference (INDICON), pp. 1-4

S , Sethuraman , Lingambudi A., Wright K., Saurabh A., Kim K.-H., Becker D., 2014, Vref optimization in DDR4 RDIMMs for improved timing margins, 2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), pp. 73-76

Gupta A., Kumar A., Chhabra M., 2011, Characterizing Pattern Dependent Delay Effects in DDR Memory Interfaces, 2011 Asian Test Symposium, pp. 425-431

Kim D., Kim H., Eo Y., 2012, Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 10, pp. 1536-1545

Querbach B., Puligundla S., Becerra D., Schoenborn Z.T., Chiang P., 2013, Comparison of hardware based and software based stress testing of memory IO interface, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 637-640

Kim Y., Kang S.C., Lee S.K., Jung U., Kim S.M., Lee B.H., 2016, Hot-Carrier Instability of nMOSFETs under Pseudorandom Bit Sequence Stress, IEEE Electron Device Letters, Vol. 37, No. 4, pp. 366-368

Garcia-Mora D.M., Garcia-Huanaco J., Zuniga-Marquez V.J., Franco-Tinoco C.J., Yahyaei-Moayyed F., Unger K.S., 2018, Power Delivery Network Impedance Characterization for High Speed I/O Interfaces using PRBS Transmissions, IEEE Electromagnetic Compatibility Magazine, Vol. 7, No. 1, pp. 87-91

van de Goor A.J., 1998, Testing Semiconductor Memories: Theory and Practice, 1st ed., John Wiley & Sons Inc.

Ciletti M.D., 2010, Advanced Digital Design with the Verilog HDL, 2nd ed., Pearson

van de Goor A.J., Schanstra I., 2002, Address and data scrambling: causes and impact on memory tests, Proc. First IEEE International Workshop on Electronic Design, Test and Applications, pp. 128-136