Mobile QR Code QR CODE

REFERENCES

1 
Wu X., Palmers P., Steyaert M. S. J., 2008, A 130nm CMOS 6bit full Nyquist 3GS/s DAC, IEEE Journal of Solid-State Circuits, Vol. 43, pp. 2396-2408DOI
2 
Greshishchev Y.M., Pollex D., Wang S.C., Besson M., Flemeke P., Szilagyi S., Aguirre J., Falt C., Hamida N.B., Gibbins R., Schvan P., 2011, A 56GS/s 6b DAC in 65nm CMOS with 256x6b memory, 2011 IEEE International Solid-State Circuits Conference, pp. 194-196DOI
3 
Nagatani M., Nosaka H., Sano K., Murata K., Kurishima K., Ida M., 2011, A 60-GS/s 6bit DAC in 0.5mm InP HBT Technology for optical communication systems, 2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), pp. 1-4DOI
4 
Kwon Y. G., Lee S. H., Jeon Y. D., Kwon J. K., 2010, A 6b 1.4GS/s 11.9mW 0.11mm2 65nm CMOS DAC with a 2-D INL bounded switching scheme, 2010 International SoC Design Conference, pp. 198-200DOI
5 
Chen R. L., Chang S. J., 2012, A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications, IEEE Transactions on Circuit And Systems—II: Express Briefs, Vol. 59, pp. 746-750DOI
6 
Chen R. L., Chang S. J., 2009, A 5-bit 1.35-GSPS DAC for UWB Transceivers, 2009 IEEE International Conference on Ubiquitous Wireless Broadband, pp. 175-179DOI
7 
Bosch A. V., Borremans M. A. F., Steyaert M. S. J., Sansen W., 2001, A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter, IEEE Journal of Solid-State Circuits, Vol. 36, pp. 315-324DOI
8 
Cong Y., Geiger R. L., 2002, Formulation of INL and DNL yield estimate on incurrent-steering D/A converter, 2002 IEEE International Symposium on Circuits and Systems. Proceedings, Vol. 3, pp. 149-152DOI
9 
Wikner J. J., Tan N., 1999, Modeling of CMOS Digital-to-Analog Converters for Telecommunication, IEEE transactions on circuits and systems-II: Analog and Digital Signal Processing, Vol. 46, pp. 489-499DOI
10 
Bosch A. V., Steyaert M. S. J., Sansen W., 2000, An accurate statistical yield model for CMOS current-steering D/A converters, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings, Vol. 4, pp. 105-108DOI
11 
Seo D., 2007, A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for Baseband Wireless Transmitter, IEEE Journal of Solid-State Circuits, Vol. 42, pp. 486-495DOI
12 
Doris K., Roermund A. H. M., 2006, Wide-bandwidth high dynamic range D/A converters, Springer, Boston, MAGoogle Search
13 
Razavi B., Chen G., Cheng J., Zhang R., 2002.12, Design of Analog CMOS Intergrated Circuits, Xian Jiaotong University Press, Xian, China, pp. 177Google Search
14 
Zhang Q., Jiang Y., Wan S., Li P., Zhang T., 2016, An integrated low jitter PLL for high speed high resolution DACs, 2016 International Conference on Integrated Circuits and Microsystems (ICICM), pp. 172-175DOI
15 
Radulov G. I., Quinn P. J., Roermund A. H. M., 2015, A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, pp. 44-53DOI
16 
Kim S. N., Kim M. R., Sung B. R. S., Kang H. W., Cho M. H., Ryu S. T., 2016, A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038mm2, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 24, pp. 794-798DOI
17 
Kim S.N., Kim W., Lee C.K., Ryu S.T., 2012, A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure, Journal of Semiconductor Technology and Science, Vol. 12, pp. 270-277DOI