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“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

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REFERENCES

1 
Ou-Yang Y.-H., Tang K.-T., 2019, An Energy-Efficient SAR ADC With Event-Triggered Error Correction, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 66, No. 5, pp. 723-727DOI
2 
Zhang H., Zhang H., Song Y., Zhang R., 2019, A 10-Bit 200-kS/s 1.76-μW SAR ADC With Hybrid CAP-MOS DAC for Energy-Limited Applications, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, No. 5, pp. 1716-1727DOI
3 
Liu M., van Roermund A. H. M., Harpe P., 2019, A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver, IEEE Journal of Solid-State Circuits, Vol. 54, No. 2, pp. 417-427DOI
4 
Rabuske F., Rabuske T., Fernandes and J., 2017, A 5-bit 300–900-MS/s 0.8–1.2-V Supply Voltage ADC With Background Self-Calibration, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64, No. 1, pp. 1-5DOI
5 
Mao J. J., Guo M. Q., Sin S. W., Martins R. P., Oct, 2018, A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current, Ieee Transactions on Circuits and Systems Ii-Express Briefs, Vol. 65, No. 10, pp. 1380-1384DOI
6 
Zhou D., Briseno-Vidrios C., Jiang J., Park C., Liu Q., Soenen E. G., Kinyua M., Silva-Martinez J., 2019, A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, No. 9, pp. 3373-3383DOI
7 
Lee C. C., Flynn M. P., 2011, A SAR-Assisted Two-Stage Pipeline ADC, IEEE Journal of Solid-State Circuits, Vol. 46, No. 4, pp. 859-869DOI
8 
Lee H.-Y., Lee B., Moon U.-K., pp 474-476, A 31.3fJ/conversion-step 70.4 dB SNDR 30MS/s 1.2V two-step pipelined ADC in 0.13μm CMOS, in 2012 IEEE International Solid-State Circuits Conference, Vol. , No. , pp. -DOI
9 
Gregoire B. R., Moon U.-K., 2008, An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain, IEEE Journal of Solid-State Circuits, Vol. 43, No. 12, pp. 2620-2630DOI
10 
Hai N., Nairn D. G., pp 1-4, A low power 12-bit 10MS/s algorithmic ADC, in Ccece 2010DOI
11 
Harpe P. J. A., Zhou C., Bi Y., van der Meijs N. P., Wang X., Philips K., Dolmans G., de Groot H., 2011, A 26 μW 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios, IEEE Journal of Solid-State Circuits, Vol. 46, No. 7, pp. 1585-1595DOI
12 
Kim Y.-M., Park J.-S., Shin Y.-J., Lee S.-H., 2014, An 87 fJ/conversion-step 12 b 10 MS/s SAR ADC using a minimum number of unit capacitors, Analog Integrated Circuits and Signal Processing, Vol. 80, No. 1, pp. 49-57DOI