Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. 2020-06 (Vol.20 No.03)
  4. 10.5573/JSTS.2020.20.3.271
XML PDF INFO REF

REFERENCES

1 
Asenov A., Sep 2003, Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs, IEEE Trans. Electron Devices, Vol. 50, No. 9, pp. 1837-1852DOI
2 
Heald R., nov. 2004, Variability in sub-100-nm SRAM designs, in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., pp. 347-352DOI
3 
Bhavnagarwala A. J., Apr 2001, The impact of intrinsic device fluctuations on CMOS SRAM cell stability, IEEE J. Solid-State Circuits, Vol. 36, No. 4, pp. 658-665DOI
4 
Abu-Rahma M. H., 2013, A methodology for statistical estimation of read access yield in SRAMs, in Nanometer variation-tolerant SRAM, 1st ed. Springer, pp. 119-153DOI
5 
Nho H., Sep 2008, Numerical estimation of yield in sub-100-nm SRAM design using Monte Carlo simulation, IEEE Trans. Circuit Syst. II, Vol. 55, No. 9, pp. 907-911DOI
6 
Kim J., Jan 2012, A novel sensing circuit for deep submicron spin transfer torque MRAM (STT-MRAM), IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 20, No. 1, pp. 181-186DOI
7 
M , Qazi , Jan 2012, A low-voltage 1 Mb FRAM in 0.13 μm CMOS featuring time-to-digital sensing for expanded operating margin, IEEE J. Solid-State Circuits, Vol. 47, No. 1, pp. 141-150DOI
8 
Xue X., May 2013, A 0.13 μm 8 Mb logic-based CuxSiyO ReRAM with self-adaptive operation for yield enhancement and power reduction, IEEE J. Solid-State Circuits, Vol. 48, No. 5, pp. 1315-1322Google Search
9 
Doorn T. S., 2008, Importance sampling Monte Carlo simulations for accurate estimation of SRAM yield, in Proc. 34th European Solid State Circuits Conf. (ESSCIRC), pp. 230-233DOI
10 
Na T., 2015, Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter, in Proc. IEEE Int. Conf. Electronics, Circuits and Syst. (ICECS), pp. 400-403DOI
11 
Na T., 2020, Tail fitting yield estimation method for resistive non-volatile memory, in IEEE Int. Conf. Electronics, Information, and Communication (ICEIC)DOI
12 
Na T., Feb 2014, Comparative study of various latch-type sense amplifiers, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 22, No. 2, pp. 425-429DOI
13 
Na T., 2015, A double-sensing-margin offset-canceling dual-stage sensing circuit for resistive nonvolatile memory, IEEE Trans. Circuits Syst. II, Vol. 62, No. 12, pp. 1109-1113DOI
14 
Kani R., 2006, Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events, in ACM/IEEE Design Automation Conference, pp. 69-72DOI
15 
Lin C. J., 2009, 45 nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell, in IEEE Int. Electron Devices Meeting (IEDM) Tech. Dig., pp. 279-282DOI
16 
Rizzo N., 2010, Toggle and spin torque: MRAM at Everspin technologies, Non-volatile Memories WorkshopGoogle Search
17 
Date T., 2010, Robust importance sampling for efficient SRAM yield analysis, in Int. Symp. Quality Electron Design (ISQED), pp. 15-21DOI
18 
Jefremow M., 2013, Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS, in Proc. Int. Solid-State Circuits Conf., pp. 216-217DOI
19 
Kim J., Mar 2014, A split-path sensing circuit for spin torque transfer MRAM (STT-MRAM), IEEE Trans. Circuits Syst. II, Vol. 61, No. 3, pp. 193-197DOI
20 
Song B., Jul 2015, Latch offset cancellation sense amplifier for deep submicrometer STT-RAM, IEEE Trans. Circuits Syst. I, Vol. 62, No. 7, pp. 1776-1784DOI
21 
Kim C., 2015, A covalent-bonded cross-coupled current-mode sense amplifier for STT-MRAM with 1T1MTJ common source-line structure array, in Proc. Int. Solid-State Circuits Conf., pp. 1-3DOI
22 
Na T., Apr 2016, An offset-tolerant dual-reference-voltage sensing scheme for deep submicrometer STT-RAM, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 24, No. 4, pp. 1361-1370DOI
23 
Trinh Q. K., Oct 2016, Novel boosted-voltage sensing scheme for variation-resilient STT-MRAM read, IEEE Trans. Circuits Syst. I, Vol. 63, No. 10, pp. 1652-1660DOI
24 
Kang W., Jan 2017, A dynamic dual-reference sensing scheme for deep submicrometer STT-MRAM, IEEE Trans. Circuits Syst. I, Vol. 64, No. 1, pp. 122-132DOI
25 
Na T., Feb 2017, Offset-canceling current-sampling sense amplifier for resistive nonvolatile memory in 65 nm CMOS, IEEE J. Solid-State Circuits, Vol. 52, No. 2, pp. 496-504DOI
26 
Dong Q., Jan 2019, A 1-Mb 28-nm 1T1MTJ STT-MRAM with single-cap offset-cancelled sense amplifier and in situ self-write-termination, IEEE J. Solid-State Circuits, Vol. 54, No. 1, pp. 231-239DOI
27 
Na T., Nov 2019, Offset-canceling single-ended sensing scheme with one-bit-line precharge architecture for resistive nonvolatile memory in 65-nm CMOS, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 27, No. 11, pp. 2548-2555DOI