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“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

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REFERENCES

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Vashchenko V., Concannon A., ter Beek M., Hopper P., 2004, High holding voltage cascaded LVTSCR structures for 5.5-V tolerant ESD protection clamps, IEEE Trans. on Devices. and Materials Reliability., Vol. 4, pp. 273-280DOI
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Ker M.-D., Hsu K.-C., 2005, Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits, IEEE Trans. Device Mater. Rel, Vol. 5, No. 2, pp. 235-249DOI
4 
Vashchenko V., Concannon A., ter Beek M., Hopper P., 2004, High holding voltage cascaded LVTSCR structure for 5.5-V tolerant ESD protection clamps, IEEE Transaction on Device and Materials Reliability, pp. 273-280Google Search
5 
Do K. I., Lee B. S., 2019, A New Dual-Direction SCR With High Holding Voltage and Low Dynamic Resistance for 5 V Application, IEEE Journal of the Electron Devices Society, Vol. 7, pp. 601-605DOI
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Salcedo J. A., Liou J. J., Liu Z., Vinson J. E., 2007, TCAD Methodology for Design of SCR Devices for Electrostatic Discharge (ESD) Applications, IEEE Transactions on Electron Devices, Vol. 54, No. 4, pp. 822-832DOI
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Ground E., Hernandez M., Sept 16-21, 2007, Obtaining TLP-like Information from an HBM Simulator, presented at the EOS/ESD Symp. Anaheim, CA, USA, pp. 2A.3-1-2A.3-7DOI
8 
Concannon A., Vashchenko V. A., ter Beek M., Hopper P., 2003, A device level negative feedback in the emitter line of SCR-structures as a method to realize latch-up free ESD protection, 2003 IEEE International Reliability Physics Symposium Proceedings. 2003. 41st Annual, pp. 105-111DOI
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Do K. I., Koo Y. S., 2020, A New SCR Structure With High Holding Voltage and Low ON-Resistance for 5-V Applications, IEEE Transactions on Electron Devices, Vol. 67, No. 3, pp. 1052-1058DOI
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Kaufmann M., Ostermann T., 2015, Simulation model based on JEDEC JS-001-2014 for circuit simulation of HBM ESD pulses on IC level, 2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits, pp. 202-206DOI
11 
Do K. I., Lee B. S., Koo Y. S., 2018, Study on 4H-SiC GGNMOS Based ESD Protection Circuit With Low Trigger Voltage Using Gate-Body Floating Technique for 70-V Applications, IEEE Electron Device Letters, Vol. 40, No. 2, pp. 283-286DOI