Mobile QR Code QR CODE

REFERENCES

1 
Virtex-5 FPGA Configuration User Guide UG071 , https://www.xilinx.com/Google Search
2 
Moradi A., Oct 2011, On the vulnerability of FPGA bitstream encryption against power analysis attacks, in Proc of the Conf on Computer and Communications Security, pp. 111-124DOI
3 
Yu H., Lee H., Lee S., Kim Y., Lee H. M., 2018, Recent Advances in FPGA Reverse Engineering, Electronics, Vol. 7, No. 10, pp. 246DOI
4 
Facon A., Guilley S., Ngo X. T., Perianin T., Mar 2019, Hardware-enabled AI for Embedded Security: A New Paradigm, in Proc of the 3rd International Conference on Recent Advances in Signal Processing Telecommunications & Computing (SigTelCom 2019), pp. 80-84DOI
5 
Malhotra S., Borer T., Singh D., Brown S., Dec 2004, The Quartus University Interface Program Enabling advanced FPGA research, in Proc of the IEEE International Conference on Field-Programmable Technology, pp. 225-230DOI
6 
Lee J. K., 2012, Verilog functional model extraction from FPGA design data, J KIISE Comput Pract Lett, Vol. 18, pp. 380-388Google Search
7 
Tavaragiri A., Couch J., Athanas P., Feb 2011, Exploration of FPGA interconnect for the design of unconventional antennas, in Proc of the ACM/ SIGDA International Symposium on Field Programmable Gate Arrays, pp. 219-226DOI
8 
Lavin C., Dec 2010, Rapid prototyping tools for FPGA designs: Rapidsmith, in Proc of the International Conference on Field-Programmable Technology IEEE, pp. 353-356DOI
9 
Lavin C., Sep 2011, Rapidsmith: Do-it-yourself CAD tools for Xilinx FPGAs, in Proc of the International Conf. on Field Programmable Logic and Applications, pp. 349-355DOI
10 
Soni R. K., 2013, Open-source bitstream generation for FPGAs, Ph D dissertation Virginia TechGoogle Search
11 
Ding Z., 2013, Deriving an NCD file from an FPGA bitstream: Methodology, architecture and evaluation, Microprocess & Microsystems, Vol. 37, No. 3, pp. 299-312DOI
12 
Note J. B., Rannaud E., Feb 2008, From the bitstream to the netlist, in Proc of the International ACM/SIGDA Symposium on Field Programmable Gate Arrays (FPGA), Vol. 18, pp. 264-264Google Search
13 
Benz F., Seffrin A., Huss S. A., Aug 2012, Bil: A tool-chain for bitstream reverse-engineering, in Proc of the International Conf on Field Programmable Logic and Applications (FPL), pp. 735-738DOI
14 
Zhang T., Wang J., Guo S., Chen Z., 2019, A comprehensive FPGA reverse engineering tool-chain: From bitstream to RTL code, in Proc of IEEE Access, pp. 38379-38389DOI
15 
Choi S., Park J., Yoo H., Jan 2020, Reverse Engineering for Xilinx FPGA chips using ISE Design Tools, Journal of Integrated Circuits and Systems, Vol. 6, No. 1Google Search
16 
Choi S., Yoo H., 2020, Fast Logic Function Extraction of LUT from Bitstream in Xilinx FPGA, Electronics, Vol. 9, No. 7, pp. 1132DOI
17 
Jeong M., May 2018, Extract LUT logics from a downloaded bitstream data in FPGA, in Proc of 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5DOI
18 
Project X-Ray , June 2020, Available online: https://prjxray.readthedocs.io/en/latest/Google Search
19 
Project IceStorm , June 2020, Available online: http://www.clifford.at/icestorm/Google Search
20 
A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs , June 2020, Available online: https://media.ccc.de/v/32c3-7139-a\_free\_and\_open\_source\_verilog-to-bitstream\_flow\_for\_ice40\_fpgas/Google Search
21 
Project X-Ray , June 2020, Documenting the Xilinx 7-series bit-stream format. Available online: https://github.com/SymbiFlow/prjxray/Google Search
22 
Project X-Ray , June 2020, Available online: https://symbiflow.github.io/prjxray-db/Google Search