Mobile QR Code QR CODE

REFERENCES

1 
Park J. S., An T. J., Ahn G. C., Lee S. H., Jul 2019, A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching and Shared Ring Amplifier, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 66, No. 7, pp. 1119-1123DOI
2 
Misra G., Agarwal A., Misra S., Agarwal K., Oct 2016, Device to device millimeter wave communication in 5G wireless cellular networks (A next generation promising wireless cellular technology), International Conference on Signal Processing, Communication, Power and Embedded System (SCOPES), pp. 89-93DOI
3 
Kim H., Oct 2016, A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs, IEEE J. of Solid-State Circuits, Vol. 51, No. 10, pp. 2262-2273DOI
4 
Wong S., Chio U., Zhu Y., Sin S., U S., Martins R. P., Aug 2013, A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC, IEEE J. of Solid-State Circuits, Vol. 48, No. 8, pp. 1783-1794DOI
5 
Liang Y., Ding R., Zhu Z., Sept 2018, A 9.1ENOB 200MS/s Asynchronous SAR ADC With Hybrid Single-Ended/Differential DAC in 55-nm CMOS for Image Sensing Signals, IEEE Sensors Journal, Vol. 18, No. 17, pp. 7130-7140DOI
6 
Liu C., Kuo C., Lin Y., Nov 2015, A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS, IEEE J. of Solid-State Circuits, Vol. 50, No. 11, pp. 2645-2654DOI
7 
Kuo H. -L., Lu C. -W., Chen P., 2021, An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC, in IEEE Access, Vol. 9, pp. 5651-5669DOI
8 
Hong H. K., Feb 2015, A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC, IEEE J. Solid-State Circuits, Vol. 50, No. 2, pp. 543-555DOI
9 
Li D., Zhu Z., Ding R., Yang Y., Nov 2018, A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 65, No. 11, pp. 1524-1528DOI
10 
Kulkarni U. M., Parikh C., Sen S., Jan 2018, A Systematic Approach to Determining the Weights of the Capacitors in the DAC of a Non-binary Redundant SAR ADCs, International Conference on VLSI Design and International Conference on Embedded Systems (VLSID), pp. 1-6DOI
11 
Park J. S., Kim D. H., An T. J., Kim M. K., Ahn G. C., Lee S. H., Feb 2020, 12 b 50 MS/s 0.18 μm CMOS SAR ADC based on highly linear C-R hybrid DAC, IET (The Institution of Engineering and Technology) Electronics Letters, Vol. 56, No. 3, pp. 119-121Google Search
12 
van Elzakker M., van Tuijl E., Geraedts P., Schinkel D., Klumperink E. A. M., Nauta B., May 2010, A 10-bit Charge-Redistribution ADC Consuming 1.9µW at 1 MS/s, IEEE J. Solid-State Circuits, Vol. 45, No. 5, pp. 1007-1015DOI
13 
Bindra H. S., Lokin C. E., Schinkel D., Annema A., Nauta B., July 2018, A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise, IEEE J. Solid-State Circuits, Vol. 53, No. 7, pp. 1902-1912DOI
14 
An T. J., Cho Y. S., Park J. S., Ahn . C., Lee S. H., Oct 2017, A Two-channel 10b 160MS/s 28nm CMOS Asynchronous Pipelined-SAR ADC with Low Channel Mismatch, Journal of Semiconductor Technology and Science, Vol. 17, No. 5, pp. 636-647Google Search
15 
Harpe P. J. A., July 2011, A 26 μW 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios, IEEE J. Solid-State Circuits, Vol. 46, No. 7, pp. 1585-1595DOI
16 
Roh Y. -J., Chang D. -J., Ryu S. -T., Dec 2020, A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 67, No. 12, pp. 2833-2837DOI
17 
Chung Y., Hsu Y., July 2019, A 12-Bit 100-MS/s Subrange SAR ADC With a Foreground Offset Tracking Calibration Scheme, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 66, No. 7, pp. 1094-1098DOI