Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. 2021-10 (Vol.21 No.05)
  4. 10.5573/JSTS.2021.21.5.297
XML PDF INFO REF

REFERENCES

1 
Son W.-S., Seo Y. K., Kim W.-J., Kim H.-N., Aug 2018, Analysis of signal transmission methods for rapid searching in active SONAR systems, J. IEIE, Vol. 55, No. 8, pp. 83-93DOI
2 
Lin Y., Feb. 2019, A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, pp. 330-332DOI
3 
Zhuang. H., June 2019, A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting, IEEE J. Solid-State Circuits, Vol. 54, No. 6, pp. 1636-1647DOI
4 
Liu. J., Feb. 2020, A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error,, San Francisco, Vol. ca, No. usa, pp. 158-160DOI
5 
Jie L., Zheng. B., Flynn M. P., Dec 2019, A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC, IEEE J. Solid-State Circuits, Vol. 54, No. 12, pp. 3386-3395DOI
6 
Salgado G. M., O’Hare D., O’Connell I., Exp Briefs, Recent advances and trends in noise shaping SAR ADCs, IEEE Trans. Circuits Syst. II, Vol. 68, No. 2, pp. 545-549DOI
7 
Zhuang. H., Jun 2019, A second-order noise-shaping SAR ADC with passive integrator and tri-level voting, IEEE J. Solid-State Circuits, Vol. 54, No. 6, pp. 1636-1647DOI
8 
Hesener. M., Feb. 2007, A 14b 40 MS/s Redundant SAR ADC with 480 MHz Clock in 0.13 pm CMOS, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, pp. 248-249DOI
9 
Hariprasath. V., April 2010, Merged capacitor switching based SAR ADC with highest switching energy-efficiency, Electronics Letters, Vol. 46, pp. 620-621Google Search
10 
Shinkel. D., Feb. 2007, A double-tail latch-type voltage sense amplifier with 18ps Setup+Hold time, in Proc. IEEE Int. Solid-State Circuits Conf., Vol. dig. tech. papers, pp. 314-315DOI
11 
Chen S.-W. M., Brodersen R. W., Dec 2006, A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13 CMOS, IEEE J. Solid-State Circuits, Vol. 41, No. 12, pp. 2669-2680DOI
12 
Liu. C.-C., Apr 2010, A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure, IEEE J. Solid-State Circuits, Vol. 45, No. 4, pp. 731-740DOI
13 
Abo A. M., Gray P. R., May 1999, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter, IEEE J. Solid-State Circuits, Vol. 34, No. 5, pp. 599-606DOI