Reuben John, 2012, Clock frequency doubler circuit for multiple frequencies and its application in a CDN to reduce power, International Conference on Computing, Electronics and Electrical Technologies, pp. 752-756

Hsueh Yu-Li, 2014, A 0.29 mm${^2}$ Frequency Synthesizer in 40nm CMOS with 0.19psrms Jitter and <-100dBc Reference Spur for 802.11ac, IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 472-473

Wu Wanghua, 2019, A 28-nm 75-fsrms Analog Fractional-N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction, IEEE Journal of Solid-State Circuits, pp. 1-12

Min Y.-J., Aug 2012, A 0.31–1 GHz fast-corrected duty-cycle corrector with successive approximation register for DDR DRAM applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 20, No. 8, pp. 1524-1528

Jeong C.H., Jan 2016, All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 24, No. 1, pp. 363-367

Raja Immanuel, May 2016, A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 24, No. 5, pp. 1975-1983

Kang K.T., Dec 2018, A 0.33–1 GHz Open-Loop Duty Cycle Corrector With Digital Falling Edge Modulator, IEEE Trans. Circuits Syst. II, Exp. Briefs, Vol. 65, No. 12, pp. 1949-1953