Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. 2021-12 (Vol.21 No.06)
  4. 10.5573/JSTS.2021.21.6.472
XML PDF INFO REF

REFERENCES

1 
Lim S., Woo Kim J., Yoon K., Lee S., Feb 2013, A 12-b Asynchronous SAR Type ADC for Bio Signal Detection, J. Semiconductor Technology and Science, Vol. 13, No. 2, pp. 108-113DOI
2 
Kim B., Yan L., Yoo J., Yoo H.-J., Jan 2011, A 40fJ/c-s 1 V 10 bit SAR ADC with Dual Sampling Capacitive DAC Topology, J. Semiconductor Technology and Science, Vol. 11, No. 1, pp. 23-32DOI
3 
Fredenburg J. A., Flynn M. P., Dec 2012, A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC, IEEE J. of Solid-State Circuits, Vol. 47, No. 12, pp. 2898-2904DOI
4 
Chen Z., Miyahara M., Matsuzawa A., A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC, Digest of 2015 Symp. on VLSI Circuits, pp. c64-C65DOI
5 
Li S., Qiao B., Gandara M., Pan D. Z., Sun N., Dec 2018, A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure, IEEE J. of Solid-State Circuits, Vol. 53, No. 12, pp. 3484-3496DOI
6 
Guo W., Zhuang H., Sun N., A 13b-ENOB 173dB-FoM 2nd-order NS SAR ADC with Passive Integrators, Digest of 2017 Symp. on VLSI Circuits 2017, pp. c236-C237DOI
7 
Hwang Y., Song Y., Park J., Jeong D., A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS, Digest of 2018 IEEE Asian Solid-State Circuits Conf. (A-SSCC), pp. 247-248DOI
8 
Park J.-S., An T.-J., Cho S.-H., Kim Y.-M., Ahn G.-C., Roh J.-H., Lee M.-K., Nah S.-P., Lee S.-H., Feb 2014, A 12b 100 MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs, J. Semiconductor Technology and Science, Vol. 14, No. 2, pp. 189-197DOI
9 
Chung H., Mar 2016, ADC-Based Backplane Receivers: Motivations, Issues and Future, J. Semiconductor Technology and Science, Vol. 16, No. 4, pp. 300-311DOI
10 
Jie L., Zheng B., Flynn M. P., Dec 2019, A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC, IEEE Journal of Solid-State Circuits, Vol. 54, No. 12, pp. 3386-3395DOI
11 
Hong H., Feb 2015, A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC, IEEE J. Solid-State Circuits, Vol. 50, No. 2, pp. 543-555DOI
12 
Luo J., April 2020, A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC, IEEE Trans. Circuits and Systems I: Regular Papers, Vol. 67, No. 4, pp. 1136-1148DOI
13 
Liu C.-C., Huang Y.-T., Huang G.-Y., Chang S.-J., Huang C.-M., Huang C.-H., Automation and Test, A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-µm digital CMOS process, 2009 Inter. Symp. on VLSI Design, Automation and Test, pp. 215-218DOI
14 
Li D., Zhu Z., Liu J., Zhuang H., Yang Y., Sun N., Nov 2020, A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration, IEEE J. of Solid-State Circuits, Vol. 55, No. 11, pp. 3051-3063DOI
15 
Miyahara M., Asada Y., Paik D., Matsuzawa A., A low-noise self-calibrating dynamic comparator for high-speed ADCs, Digest of 2008 IEEE Asian Solid-State Circuits Conf. (A-SSCC), pp. 269-272DOI
16 
van Elzakker M., van Tuijl E., Geraedts P., Schinkel D., Klumperink E. A. M., Nauta B., May 2010, A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s, IEEE J. Solid-State Circuits, Vol. 45, No. 5, pp. 1007-1015DOI