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“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

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References

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Straayer M. Z., Perrott M. H., Jun. 2007, A 10-bit 20MHz 38mW 950MHz CT ΔΣ ADC with a 5-bit noise-shaping VCO-based quantizer and DEM circuit in 0.13u cmos, 2007 IEEE Symposium on VLSI Circuits, pp. 246-247DOI
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Park M., Perrott M. H., Dec. 2009, A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time ΔΣ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 μm CMOS, IEEE Journal of Solid-State Circuits, Vol. 44, No. 12, pp. 3344-3358DOI
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Lee K., Yoon Y., Sun N., Dec. 2007, A Scaling-Friendly Low-Power Small-Area ΔΣ ADC With VCO-Based Integrator and Intrinsic Mismatch Shaping Capability, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 5, No. 4, pp. 561-573DOI
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7 
Li S., Mukherjee A., Sun N., Jul. 2017, A 174.3-dB FoM VCO-Based CT ΔΣ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS, IEEE Journal of Solid-State Circuits, Vol. 52, No. 7, pp. 1940-1952DOI
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Zhong Y., et al. , Feb. 2020, A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS, IEEE Journal of Solid-State Circuits, Vol. 55, No. 2, pp. 356-368DOI
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Maghami H., et al. , Mar. 2020, A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique, IEEE Journal of Solid-State Circuits, Vol. 55, No. 3, pp. 706-718DOI
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Kim T., Han C., Maghari N., Dec. 2017, A 4th-Order Continuous-Time Delta-Sigma Modulator Using 6-bit Double Noise-Shaped Quantizer, IEEE Journal of Solid-State Circuits, Vol. 52, No. 12, pp. 3248-3261DOI
11 
Honarparvar M., de la Rosa J. M., Sawan M., Sep. 2020, A 10-MHz BW 77.3-dB SNDR 640-MS/s GRO-Based CT MASH ΔΣ Modulator, IEEE Transactions on Circuits and Systems-II, Vol. 67, No. 9, pp. 1519-1523DOI