Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. 2022-12 (Vol.22 No.06)
  4. 10.5573/JSTS.2022.22.6.452
XML PDF INFO REF

References

1 
Hong S., 2010, Memory technology trend and future challenges, 2010 International Electron Devices Meeting, pp. 12.4.1-12.4.4DOI
2 
Duvvury C., Nov. 1986, A guide to short-channel effects in MOSFETs, in IEEE Circuits and Devices Magazine, Vol. 2, No. 6, pp. 6-10DOI
3 
Park S., 2015, Technology Scaling Challenge and Future Prospects of DRAM and NAND Flash Memory, 2015 IEEE International Memory Workshop (IMW), pp. 1-4DOI
4 
Lee Jin-sung., Park Jin-hyo., Kim Geon., Choi Hyun D., Lee Myoung J., 2020, Partial Isolation Type Buried Channel Array Transistor (Pi-BCAT) for a Sub-20 nm DRAM Cell Transistor, Electronics, Vol. 9, No. 11: 1908DOI
5 
Kim J. V., et al. , 2005, S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond, Digest of Technical Papers. 2005 Symposium on VLSI Technology, pp. 34-35DOI
6 
Mueller W., et al. , 2005, Challenges for the DRAM cell scaling to 40nm, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest, pp. 4-339DOI
7 
Kim J. Y., et al. , 2003, The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407), pp. 11-12DOI
8 
Yu J., Aflatooni K., 2006, Leakage Current in DRAM Memory Cell, 2006 16th Biennial University/Government/Industry Microelectronics Symposium, pp. 191-194DOI
9 
Saino K., et al. , 2000, Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138), pp. 837-840DOI
10 
Gautam S. K., Maheshwaram S., Manhas S. K., Kumar A., Jo S. Sherman and S. H., 2016, Reduction of GIDL Using Dual Work-Function Metal Gate in DRAM, 2016 IEEE 8th International Memory Workshop (IMW), pp. 1-4DOI
11 
Kulkarni P., et al. , 2011, Impact of substrate bias on GIDL for thin-BOX ETSOI devices, 2011 International Conference on Simulation of Semiconductor Processes and Devices, pp. 103-106DOI
12 
Uematsu M., 1996, Simulation of boron diffusion in Si based on the kick-out mechanism, 1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095), pp. 25-26DOI