Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. 2023-02 (Vol.23 No.01)
  4. 10.5573/JSTS.2023.23.1.64
XML PDF INFO REF

References

1 
S. Okhonin, et al., “A Capacitor-less SOI 1T-DRAM concept,” IEEE Int. SOI Conf., pp. 153-154, 2001.DOI
2 
T. Osawa, et al., “Memory Design Using a One-Transistor Gain Cell on SOI,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1510-1522, 2002.DOI
3 
C. Kuo, et al., “A Capacitorless Double-Gate DRAM Cell Design for High Density Applications,” IEDM Tech. Dig., pp. 843-846, Dec. 2002.DOI
4 
S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, “A capacitor-less 1T-DRAM cell,” IEEE Electron Device Lett., vol. 23, no. 2, pp. 85-87, Feb. 2002.DOI
5 
C. Kuo, T.-J. King, and C. Hu, “A capacitorless double gate DRAM technology for sub-100-nm embedded and stand-alone memory applications,” IEEE Trans. Electron Devices, vol. 50, no. 12, pp. 2408-2416, Dec. 2003.DOI
6 
J. H. Seo, Y. J. Yoon, E. Yu, W. Sun, H. Shin, I. M. Kang, J.-H. Lee, and S. Cho, “Fabrication and Characterization of a Thin-Body Poly-Si 1T DRAM with Charge-Trap Effect,” IEEE Electron Device Lett., vol. 40, no. 4, pp. 566-569, Apr. 2019.DOI
7 
Md. H. R. Ansari, N. Navlakha, J. Y. Lee, and S. Cho, “Double-Gate Junctionless 1T DRAM With Physical Barriers for Retention Improvement,” IEEE Trans. Electron Devices, vol. 67, no. 4, pp. 1471-1479, Apr. 2020.DOI
8 
Md. H. R. Ansari and S. Cho, “Performance Improvement of 1T DRAM by Raised Source and Drain Engineering,” IEEE Trans. Electron Devices, vol. 68, no. 4, pp. 1577-1584, Apr. 2021.DOI
9 
Y. J. Yoon, J. H. Seo, S. Cho, J.-H. Lee, and I. M. Kang, “A polycrystalline-silicon dual-gate MOSFET-based 1-T DRAM using grain boundary-induced variable resistance,” Appl. Phys. Lett., vol. 114, no. 18, pp. 183503-1-183503-5, May 2019.DOI
10 
J.-T. Lin, H.-H. Lin, Y.-J. Chen, C.-Y. Yu, A. Kranti, C.-C. Lin, and W.-H. Lee, “Vertical transistor with n-bridge and body on gate for low-power 1T-DRAM application,” IEEE Trans. Electron Devices, vol. 64, no. 12, pp. 4937-4945, Dec. 2017.DOI
11 
E. Yoshida and T. Tanaka, “A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 692-697, Apr. 2006.DOI
12 
E. Yu, S. Cho, H. Shin, and B.-G. Park, “A Band-Engineered One-Transistor DRAM with Improved Data Retention and Power Efficiency,” IEEE Electron Device Lett., vol. 40, no. 4, pp. 562-565, Apr. 2019.DOI
13 
N. Navlakha, J.-T. Lin, and A. Kranti, “Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering,” J. Appl. Phys., vol. 119, no. 21, 214501, Jun. 2016.DOI
14 
E. Yu, S. Cho, K. Roy, and B.-G. Park, “A Quantum-Well Charge-Trap Synaptic Transistor with Highly Linear Weight Tunability,” IEEE J. Electron Devices Soc., vol. 8, pp. 834-840, Aug. 2020.DOI
15 
M. G. Ertosun, P. Kapur, and K. C. Saraswat, “A highly scalable capacitorless double gate quantum well single transistor DRAM: 1T-QW DRAM,” IEEE Electron Device Lett., vol. 29, no. 12, pp. 1405-1407, Dec. 2008.DOI
16 
A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, pp. 329-337, Nov. 2011.DOI
17 
Colombo, Luciano, R. Resta, and S. Baroni, “Valence-band offsets at strained Si/Ge interfaces,” Phys. Rev. B, vol. 44, no. 11, 5572, 1991.DOI
18 
Almeida, L. Mendes, et al., “Optimizing the front and back biases for the best sense margin and retention time in UTBOX FBRAM,” Solid-State Electron., vol. 90, pp. 149-154, 2013.DOI
19 
A. Pal, A. Nainani, S. Gupta, and K. C. Saraswat, “Performance improvement of one-transistor DRAM by band engineering,” IEEE Electron Device Lett., vol. 33, no. 1, pp. 29-31, Jan. 2012.DOI