Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. 2023-10 (Vol.23 No.05)
  4. 10.5573/JSTS.2023.23.5.283
XML PDF INFO REF

References

1 
E. Cahill, B. Hutchings, and J. Goeders, "Approaches for FPGA design assurance," ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 15, no. 3, pp. 1-29, 2021.DOI
2 
J. Yoon et al., "A bitstream reverse engineering tool for FPGA hardware trojan detection," in Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, 2018, pp. 2318-2320.DOI
3 
J. Speith, F. Schweins, M. Ender, M. Fyrbiak, A. May, and C. Paar, "How Not to Protect Your IP-An Industry-Wide Break of IEEE 1735 Implementations," in 2022 IEEE Symposium on Security and Privacy (SP), 2022: IEEE, pp. 1656-1671.DOI
4 
S. Mal-Sarkar, R. Karam, S. Narasimhan, A. Ghosh, A. Krishna, and S. Bhunia, "Design and validation for FPGA trust under hardware trojan attacks," IEEE Transactions on Multi-Scale Computing Systems, vol. 2, no. 3, pp. 186-198, 2016.DOI
5 
A. Moradi, D. Oswald, C. Paar, and P. Swierczynski, "Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering," in Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays, 2013, pp. 91-100.DOI
6 
A. Akhunzada et al., "Man-At-The-End attacks: Analysis, taxonomy, human aspects, motivation and future directions," Journal of Network and Computer Applications, vol. 48, pp. 44-57, 2015.DOI
7 
S. Choi, J. Yeo, and H. Yoo, "Extraction of ROM Data from Bitstream in Xilinx FPGA," in 2020 International SoC Design Conference (ISOCC), 2020: IEEE, pp. 97-98.DOI
8 
H. Yu, H. Lee, S. Lee, Y. Kim, and H.-M. Lee, "Recent advances in FPGA reverse engineering," Electronics, vol. 7, no. 10, p. 246, 2018.DOI
9 
F. Benz, A. Seffrin, and S. A. Huss, "Bil: A tool-chain for bitstream reverse-engineering," in 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012: IEEE, pp. 735-738.DOI
10 
S. Y. Choi, J. W. Park, and H. Y. Yoo, "Reverse engineering for Xilinx FPGA chips using ISE design tools," Journal of Integrated Circuits and Systems, vol. 6, no. 1, 2020.URL
11 
J.-B. Note and É. Rannaud, "From the bitstream to the netlist," in FPGA, 2008, vol. 8, pp. 264-264.URL
12 
Z. Ding, Q. Wu, Y. Zhang, and L. Zhu, "Deriving an NCD file from an FPGA bitstream: Methodology, architecture and evaluation," Microprocessors and Microsystems, vol. 37, no. 3, pp. 299-312, 2013.DOI
13 
T. Zhang, J. Wang, S. Guo, and Z. Chen, "A comprehensive FPGA reverse engineering tool-chain: From bitstream to RTL code," IEEE Access, vol. 7, pp. 38379-38389, 2019.DOI
14 
M. Ender, P. Swierczynski, S. Wallat, M. Wilhelm, P. M. Knopp, and C. Paar, "Insights into the mind of a trojan designer: the challenge to integrate a trojan into the bitstream," in Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019, pp. 112-119.DOI
15 
H. Yu, H.-M. Lee, Y. Shin, and Y. Kim, "FPGA reverse engineering in Vivado design suite based on X-ray project," in 2019 International SoC Design Conference (ISOCC), 2019: IEEE, pp. 239-240.DOI
16 
H. Yu, M. Cho, S. Lee, H.-M. Lee, and Y. Kim, "Multi Look-up Table FPGA Reverse Engineering with Bitstream Extraction and Multiple PIP/PLP Matching," Journal of Semiconductor Technology and Science, vol. 21, no. 1, pp. 49-61, 2021.DOI
17 
Zynq-7000 All Programmable SoC Architecture Porting Quick Start Guide. Available online: https://www.xilinx.com (accessed on 8 December 2021).URL
18 
Kintex7 FPGA Family product brief. Available online: https://www.xilinx.com/kintex7 (accessed on 8 December 2021).URL
19 
A. Chhotaray, A. Nahiyan, T. Shrimpton, D. Forte, and M. Tehranipoor, "Standardizing bad cryptographic practice: A teardown of the IEEE standard for protecting electronic-design intellectual property," in Proceedings of the 2017 ACM SIGSAC conference on computer and communications security, 2017, pp. 1533-1546.DOI
20 
Lattice Radiant Software 3.0 User Guide. Available online: https://www.latticesemi.com/view_document?document_id=53229 (accessed on 8 December 2021).URL
21 
Carbon cypher mrexodia and Mattiwatti. Available online: https://github.com/x64dbg/ScyllaHide(accessed on 9 December 2021).URL