Mobile QR Code QR CODE

References

1 
G. Hou and B. Razavi, "A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance," Solid-State Circuits, IEEE Journal of, Vol. 57, No. 9, pp. 2856-2867, Sept., 2022DOI
2 
K. -C. Chen, W. W. -T. Kuo and A. Emami, "A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS," Solid-State Circuits, IEEE Journal of, Vol. 56, No. 3, pp. 750-762, March., 2021.DOI
3 
J. Lee, P. -C. Chiang, P. -J. Peng, L. -Y. Chen and C. - C. Weng, "Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies," Solid-State Circuits, IEEE Journal of, Vol. 50, No. 9, pp. 2061-2073, Sept., 2015.DOI
4 
H. Park, J. Sim, Y. Choi, J. Choi, Y. Kwon and C. Kim, "A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations," Solid-State Circuits, IEEE Journal of, Vol. 57, No. 2, pp. 562-572, Feb., 2022.DOI
5 
J. Im, "A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET," Solid-State Circuits, IEEE Journal of, Vol. 52, No. 12, pp. 3486-3502, Dec. 2017.DOI
6 
L. Tang, W. Gai, L. Shi, X. Xiang, K. Sheng and A. He, "A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS," Solid-State Circuits Conference, 2018. ISSCC 2018. Digest of Technical Papers. IEEE International, pp. 114-116, Feb., 2018DOI
7 
A. Roshan-Zamir et al., “A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge- Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS,” Solid-State Circuits, IEEE Journal of, Vol. 54, No. 3, pp. 672-684, Mar., 2019.DOI
8 
B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.URL
9 
Y. Choi et al., "A 25-Gb/s Single-Ended PAM Receiver With Time-Windowed LSB Decoder for High- Speed Memory Interfaces" Solid-State Cir-cuits, IEEE Journal of, Vol. 58, No. 7, pp. 2005-2015, July 2023DOI
10 
J. -M. Kim, S. Kim, I. -Y. Lee, S. -K. Han and S. -G. Lee, "A Low-Noise Four-Stage Voltage-Controlled Ring Oscillator in Deep-Submicrometer CMOS Technology," Circuits and Systems II, IEEE Transactions on, Vol. 60, No. 2, pp. 71-75, Feb. 2006.DOI
11 
J. L. Zerbe et al., "Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell," Solid-State Circuits, IEEE Journal of, Vol. 38, No. 12, pp. 2121-2130, Dec., 2003.DOI
12 
D. -H. Kwon, M. Kim, S. -G. Kim and W. -Y. Choi, "A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector," Circuits and Systems II, IEEE Transactions on, Vol. 66, No. 3, pp. 362-366, March. 2019.DOI
13 
P. -J. Peng, J. -F. Li, L. -Y. Chen and J. Lee, "6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS," Solid-State Circuits Conference, 2017. ISSCC 2017. Digest of Technical Papers. IEEE International, pp. 110-111, 2018.DOI