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“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

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References

1 
L. Tang, W. Gai, L. Shi and X. Xiang, "A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery," Symposium on Circuits and Systems, 2017. ISCAS2017. IEEE International, 28-31, pp. 1-4, May, 2017.DOI
2 
M. Verbeke, G. Torfs and P. Rombouts, "The Truth About 2-Level Transition Elimination in Bang-Bang PAM-4 CDRs," Circuits and Systems I: Regular Papers, IEEE Transactions on, Vol. 68, No. 1, pp. 469-482, Jan., 2021.DOI
3 
D. -H. Kwon, M. Kim, S. -G. Kim and W. -Y. Choi, "A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector," Circuits and Systems II: Express Briefs, IEEE Transactions on, Vol. 66, No. 3, pp. 362-366, Mar., 2019.DOI
4 
W. Jung, K. Lee, K. Park, H. Ju, J. Lee and D. -K. Jeong, "A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS," Solid-State Circuits, IEEE Journal of, Vol. 58, No. 5, pp. 1414-1424, May, 2023.DOI
5 
H. Ju, K. Lee, K. Park, W. Jung and D. -K. Jeong, "Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector," Solid-State Circuits, IEEE Journal of, Vol. 57, No. 10, pp. 3014-3024, Oct., 2022.DOI
6 
T. Li, K. Xin, J. Zhang and G. Zhang, "A Novel High-Gain PAM4 Baud-Rate Phase Detector for ADC-Based CDR," Integrated Circuits and Microsystems, 2022, ICICM2022, 7th International Conference on, 28-31, pp. 606-609, Oct, 2022.DOI
7 
S. Roh, K. Lee, M. Shim, M. -C. Choi and D. -K. Jeong, "A 64-Gb/s PAM-4 Receiver With Transition-Weighted Phase Detector," Circuits and Systems II: Express Briefs, IEEE Transactions on, Vol. 69, No. 9, pp. 3704-3708, Sept., 2022.DOI
8 
S. Park et al., "A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications," Solid-State Circuits Conference, 2023. ISSCC2023, IEEE International, 19-23, pp. 118-120, Feb., 2023.DOI
9 
G. Hou and B. Razavi, "A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance," Solid-State Circuits, IEEE Journal of, Vol. 57, No. 9, pp. 2856-2867, Sept., 2022.DOI
10 
H. Park, J. Sim, Y. Choi, J. Choi, Y. Kwon and C. Kim, "A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations," Solid-State Circuits, IEEE Journal of, Vol. 57, No. 2, pp. 562-572, Feb., 2022.DOI
11 
Y. Choi et al., "A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces," Solid-State Circuits, IEEE Journal of, Vol. 58, No. 7, pp. 2005-2015, Jul., 2023.DOI