Mobile QR Code QR CODE

The Journal of Semiconductor Technology and Science (JSTS) is an international, peer-reviewed, and open-access journal that is published bimonthly.
- Scope: semiconductor processes, devices, circuits, and MEMS.
- Editor-in-Chief: Prof. Woo Young Choi (ECE, Seoul National University)
- Indexed within Science Citation Index Expanded (SCIE), SCOPUS, Korea Citation Index (KCI), and other databases.

Journal Search

  1. Home
  2. Archive
  3. 2025-06 (Vol.25 No.03)
  4. 10.5573/JSTS.2025.25.3.199
XML PDF INFO REF

References

1 
E.-K. Jang, L. J. Kim, C. A. Lee, C. Yoon, and J.-S. Lee, ``Analysis of residual stresses induced in the confined 3D NAND flash memory structure for process optimization,'' IEEE Journal of the Electron Devices Society, vol. 10, pp. 104-108, January 2022.DOI
2 
S. S. Kim, S. K. Yong, W. Kim, S. Kang, H. W. Park, K. J. Yoon, D. S. Sheen, S. Lee, C. S. Hwnag, ``Review of semiconductor flash memory devices for material and process issues,'' Advanced Materials, vol. 35, no. 43, 2200659, March 2022.DOI
3 
T. Reiter, X. Klemenschits, and L. Filipovic, ``Impact of plasma induced damage on the fabrication of 3D NAND flash memory,'' Solid-State Electron, vol. 192, 108261, June 2022.DOI
4 
T.-H. Hsu, H.-T. Lue, P.-Y. Du, W.-C. Chen, T.-H. Yeh, and L. Lee, ``A comprehensive study of double-density hemi-cylindrical (HC) 3-D NAND flash,'' IEEE Transactions on Electron Devices, vol. 67, no. 12, pp. 5362-5367, 2020.DOI
5 
H.-T. Lue, T.-H. Yeh P.-Y. Du, R. Lo, W.-C. Chen, and T.-H. Hsu, ``A novel double-density hemi-cylindrical (HC) structure to produce more than double memory density enhancement for 3D NAND flash,'' Technical Digest - International Electron Devices Meeting (IEDM), pp. 28.2.1-28.2.4, December 2019.DOI
6 
T. Kim, C. Son, T. Park, and S. Lim, ``Oxide regrowth mechanism during silicon nitride etching in vertical 3D NAND struc-tures,'' Microelectronic Engineering, vol. 221, no. 15, pp.111191, January 2020.DOI
7 
R. Micheloni, S. Aritome, and L. Crippa, ``Array architectures for 3-D NAND flash memories,'' Proceedings of the IEEE, vol. 105, no. 9, pp. 1634-1649, September 2017.DOI
8 
S. Rachidi, A. Arreghini, D. Verreck, G. K. Donadio, K. Banerjee, and K. Katcko, ``At the extreme of 3D-NAND scaling: 25 nm Z-pitch with 10 nm word line cells,'' Proc. of 2022 IEEE International Memory Workshop (IMW), pp. 1-4, May 2022.DOI
9 
H. Aochi, ``BiCS flash as a future 3D non-volatile memory technology for ultra high density storage devices,'' Proc. of 2009 IEEE International Memory Workshop (IMW), pp. 1-2, May 2009.DOI
10 
Y.-T. Oh, K.-B. Kim, S.-H. Shin, H. Sim, N. V. Toan, T. Ono, and Y.-H. Song, ``Impact of etch angles on cell charac-teristics in 3D NAND flash memory,'' Microelectronics Journal, vol. 79, pp. 1-6, September 2018.DOI
11 
H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, and M. Kito, ``Bit cost scalable technology with punch and plug process for ultra high density flash memory,'' Proc. of 2007 IEEE Symposium on VLSI Technology, pp. 14-15, June 2007.DOI
12 
P. Moon, J. Y. Lim, T.-U. Youn, S.-K. Park, and I. Yun, ``Field-dependent charge trapping analysis of ONO inter-poly dielectrics for NAND flash memory applications,'' Solid-State Electronics, vol. 94, pp. 51-55, April 2014.DOI
13 
B. Kim, S.-H. Lim, D. W. Kim, T. Nakanishi, S. Yang, and J.-Y. Ahn, ``Investigation of ultra thin poly-crystalline silicon channel for vertical NAND flash,'' Proc. of International Reliability Physics Symposium (IRPS), pp. 2E.4.1-2E.4.4, April 2011.DOI
14 
G. van den Bosch, G. S. Kar, P. Blomme, A. Arreghini, A. Cacciato, and L. Breuil, ``Highly scaled vertical cylindrical SONOS cell with bilayer polysili-con channel for 3-D nand flash memory,'' IEEE Electron Device Letters, vol. 32, no. 11, pp. 1501-1503, November 2011.DOI
15 
T. C. Li, B. D. Reiss, S. P. Kuttiatoor, V. D. Lam, J. Lee, and R. Jia, ``CMP solutions for 3D-NAND staircase CMP,'' Proc. of International Conference on Planarization/CMP Technology 2015, ICPT 2015, pp. 1-3, September 2015.URL
16 
Y. Choi, T. Kim, H. Lee, J. Park, J. Park, D. Ryu, and W. Jeon, ``Bottom-up plasma-enhanced atomic layer deposition of SiO2 by utilizing growth inhibition using NH3 plasma pre-treatment for seamless gap-fill process,'' Scientific Reports, vol. 12, 15756, September 2022.DOI
17 
D. Tetzlaff, et al., “Introducing pinhole magnification by selective etching: application to poly-Si on ul-tra-thin silicon oxide films,” Energy Procedia, vol. 124, pp. 435–440, Sep. 2017.DOI
18 
G. Yan, P. C. H. Chan, I-M. Hsing, R. K. Sharma, J. K. O. Sin, and Y. Wang, ``An improved TMAH Si-etching solu-tion without attacking exposed aluminum,'' Sensors and Actuators A: Physical, vol. 89, No. 1-2, pp. 135-141, March 2011.DOI
19 
T. Park, T. Kim, C. Son, and S. Lim, ``Passivation of poly-Si surface using vinyl and epoxy group additives for selective Si3N4 etching in H3PO4 solution,'' Applied Surface Science, vol. 608, no. 15, 155143, January 2023.DOI
20 
A. A. Pande, D. S. L. Mui, and D. W. Hess, ``SiO2 etching with aqueous HF: Design and development of a laboratory-scale integrated wet etch/dry reactor,'' IEEE Transactions on Semiconductor Manufacturing, vol. 24, no. 1, pp. 104-116, February 2011.DOI
21 
K. F. Shariar, J. Zhang, K. Coasey, A. Sufuan, R. Remy, J. Qu, M. Mackay, and Y. Zeng, ``The effects of ICP dry etch-ing and HF wet etching on the morphology of SiO2 surface,'' Materials Research Express, vol. 5, No. 9, 095903, January 2023.DOI
22 
K. B. Sundaram, R. E. Sah, H. Baumann, K. Balachandran, and R. M. Todi, ``Wet etching studies of sil-icon nitride thin films deposited by electron cyclo-tron resonance (ECR) plasma enhanced chemi-cal vapor deposition,'' Microelectronic Engineering, vol. 70, no. 1, pp. 109-114, October 2003.DOI
23 
T. Luoh, Y. HUang, C.-M. CHen, Y.-T. Hung, L.-W. Yang, and T. Yang, ``Tungsten gate replacement process optimization in 3D NAND memory,'' Proc. of 2019 Joint International Symposium on e-Manufacturing & Design Collaboration & Semiconductor Manufacturing (ISSM), pp.1-4, September 2019.DOI
24 
Y. Noh, Y. Ahn, H. Yoo, B. Han, S. Chung, and K. Shim, ``A new metal control gate last process (MCGL process) for high performance DC-SF (dual control gate with surrounding floating gate) 3D NAND flash memory,'' Proc. of 2012 Symposium on VLSI Technology (VLSIT), pp. 19-20, June 2012.DOI
25 
U. M. Bhatt, S. K. Manhas, A. Kumar, M. Pakala, and E. Yieh, ``Mitigating the impact of channel tapering in vertical channel 3-D NAND,'' IEEE Transactions on Electron Devices, vol. 67, no. 3, pp. 929-936, March 2020.DOI