| Title |
A More Practical Indicator of MAC Operational Power Efficiency inside Memory-based Synapse Array |
| Authors |
(Seongjae Cho) ; (Sung-Tae Lee) ; (Soomin Kim) ; (Hyungcheol Shin) |
| DOI |
https://doi.org/10.5573/JSTS.2024.24.1.47 |
| Keywords |
Hardware artificial intelligence; power efficiency; multiplicate-and-accumulate (MAC) operation; memory-based artificial intelligence chip |
| Abstract |
Recently, existing software-based artificial intelligence technology is being implemented through hardware to improve area and energy efficiencies. Thus, there might be various performance indicators, but power efficiency is an important criterion for evaluating the performance of artificial intelligence chips. Currently, frequently used power efficiency indicators are for all-circuit-based artificial intelligence semiconductor chips, and for the cell-level technology-based artificial intelligence chips that can maximize power efficiency, it is difficult to use the existing indicators as they are. This study presents a practical indicator for evaluating power efficiency when implementing memory cell-based artificial intelligence semiconductor chips. Unlike conventional methodologies, the proposed performance indicators provide a clearer picture of power efficiency changes depending on what type of memory cell is used. Furthermore, the number of multiplicate-and-accumulate (MAC) operations and the number of memory cells cancel each other in the process of deriving the index, which can be a more significant indicator in the memory technology perspective in the sense that it has a greater dependence on the electrical characteristics of the memory cells themselves than on array density. |