I. INTRODUCTION

Tunnel field-effect transistor (TFET) is considered to be a promising energy-efficient switching device since they can achieve under 60 mV/decade subthreshold swing (SS)^[1]. Carrier injection mechanism in TFETs relies on band-to-band tunneling from the source to the channel. It has been reported that tunneling rate of carriers from source to channel is inversely proportional to the band gap of channel materials^[2]. Therefore, a material having a small band gap is preferred to increase the current of TFET. Recently, extensive researches have been carried out to improve the on-current. Various materials have been investigated to reduce the tunneling barrier width and height^[3-5]. Generally, Si-TFETs exhibit low on-current due to large band gap. In order to overcome large tunneling barrier, SiGe, which has a smaller band gap than that of Si, is a good alternative. In addition, SiGe is complementary MOS (CMOS) compatible because it is a group IV material^[6]. Although high Ge content is preferred for improving the on-current, it is contradictory to the process capability due to the crystal lattice mismatch with Si substrate. Generally, interface problem arises when SiGe having a high content of Ge is directly grown on Si substrate. Dislocation lines starting from interface between Si substrate and SiGe channel are shown in Fig. 1.

Fig. 1. Threading dislocation lines found at the junction of SiGe and Si due to different lattice constants.

These lines act as trap sites on the surface and degrade the mobility of carriers when current flows through the SiGe channel. To reduce the threading dislocation density (TDD) caused by the lattice mismatch, some studies have been conducted to form a trap-less channel with thick lattice matched-buffer layer^[7,8]. However, there are two problems with the thick buffer layer. First, in terms of the fabrication of a transistor, additional works are required to block the leakage path to the buffer layer. For example, it needs additional blanket stacks (SiGe/Ge/SiGe) to match lattice constant with virtual substrate^[9], which is not suitable for modern CMOS which requires thin body. Also, the thick body requires additional groundplane doping to suppress body leakage. When a TFET is fabricated, it is necessary to reduce the body leakage in the subthreshold region to obtain a low subthreshold swing (SS)^[10]. Second, when the thicker crystal layer is grown, the cost increases in proportion to the thickness. In this paper, to solve the abovementioned problems, we have proposed the formation method of a SiGe nanowire channel with graded Ge concentration. The proposed SiGe channel has high Ge concentration (about 40%) at the channel surface to boost on-current, while Ge content is low at the interface between SiGe and Si substrate to reduce the dislocation. To verify the proposed method, TCAD simulations have been performed.

II. PROPOSED FABRICATION PROCESS

The proposed nanowire device can be fabricated by the process of Fig. 2. The feasibility of the structure is verified by three dimensional (3D) TCAD process simulation as shown in Fig. 2. A two-step oxidation method (Fig. 3) is used to make a nanowire with graded Ge concentration. After active regions having narrow fins are formed by e-beam lithography, the first oxidation is performed for rounding the channel. The edges of the rectangular-shaped channel become rounded because the oxidation rate at the corner is faster than that on the flat surface. The Si atoms at the corner are more likely to encounter an oxygen molecule, so the oxidation rate is faster at the corner. The temperature and time for the first oxidation should be selected appropriately. Otherwise, the rounded shape may not be formed or the Si may be exhausted during the oxidation as can be seen in the process simulations of Fig. 4. After the first oxidation, the oxide layer which is formed by the first oxidation process is removed. Then, the epitaxial growth of 30-nm thick SiGe layer with 20% Ge concentration is carried out. Second oxidation process, called Ge condensation, is conducted. Here, the temperature at which the oxidation rate of Si is higher than that of Ge should be selected. When the Si atoms in the SiGe are selectively oxidized, the Ge diffuses into the Si channel and the Ge concentration near the channel surface increases. This Ge condensation is experimentally proved by 5 minutes oxidation under an oxygen atmosphere at 950˚C. Energydispersive x-ray spectroscopy (EDS) of Fig. 5 shows that the initial Ge content is about 20% and the Ge content of the channel surface reaches to ~40% after Ge condensation. The oxide layer formed by the second oxidation process can be used as a buffer layer in subsequent processes without stripping, and the remaining processes can be performed using the gate-last process as depicted in Fig. 2.

Fig. 2. Proposed device structure and process flow.

Fig. 3. Fabrication method of Ge condensed SiGe channel (a) Active pattern with e-beam lithography, (b) 1st oxidation for wire rounding and dHF strip, (c) Epitaxial growth of SiGe with low Ge mole fraction, (d) 2nd oxidation called Ge condensation.

Fig. 4. (a) Active Si (90 nm Width and 70 nm height) before first oxidation process, (b) Shape of active Si after oxidization, (c) Oxide thickness with various temperatures and times.

Fig. 5. Energy-dispersive x-ray spectroscopy profiles of SiGe channels.

III. SIMULATION RESULT

TFET with concentration-graded SiGe channel is simulated. Based on the EDS data of Fig. 5, Ge content is set to decrease linearly from the surface (Fig. 6). A SiGechannel TFET without Ge condensation and a Si-channel TFET are used as a control group. To simulate band to band tunneling (BTBT) generation rate (G) per unit volume at uniform electric field limit, Kane’s model is used. The coefficients in the model are obtained from the experimental data^[11]. The physical parameters of the TFETs used in this simulation are shown in Table 1. Fig. 7 indicates the 2D cross-sectional structure of the simulated TFETs. A nanowire TFET is simulated by rotating about the bottom of the Si substrate. The DC characteristics of the proposed TFET are compared to those of the SiGe-channel TFET without Ge condensation and the Si-channel TFET. Fig. 8 demonstrates that the proposed TFET has enhanced Ion and steeper SS although there is a small amount of Ioff increase. In the case of TFETs which has a fatal disadvantage of a low driving current, the small increase of Ioff is acceptable if the driving current and SS can be enhanced at the same time because Ioff can be reduced by adjusting the underlap and drain doping^[12]. The enhanced Ion and steeper SS result from the reduction of band gap with the help of Ge condensation since the tunneling are predominantly generated near the channel surface in TFETs. Fig. 9(a)-(c) show that the number of the generated tunneling carriers increases as the Ge concentration near the channel becomes higher.

Fig. 5. Energy-dispersive x-ray spectroscopy profiles of SiGe channels.

Fig. 6. The Ge contents of the SiGe channel used in the simulation tool based on experimental EDS data.

Fig. 7. Simulated TFET structures (a) SiGe with surface Gerich and gradually decreasing content from channel surface, (b) SiGe TFET with constant Ge content (The structure was drawn in 2D, and then rotated around the bottom of the Si substrate to form a nanowire structure).

Fig. 8. Transfer curves of SiGe TFETs with and without Ge condensation and Si channel TFET.

Fig. 9. Contour Diagrams of electron band to band tunneling generation according to Ge content in SiGe channel.

IV. CONCLUSION

In this study, the TFET with Ge-condensed SiGe nanowire channel is proposed to improve Ion and SS simultaneously. The proposed nanowires are formed by the two step oxidation processes; The first oxidation is the edge-rounding oxidation of rectangular-shape Si channel and the second oxidation is the Ge condensation oxidation. Based on the process and device simulations, it is concluded that the enhanced Ion and SS result from the reduction of band gap with the help of Ge condensation at the channel surface.