1. Device Structure

Fig. 1 shows three device configurations used for simulation using Synopsys SentaurusTM Device^[8]. The crystal orientation of the top/bottom surface is fixed at (001) and the channel directions < 100 > and < 110 > are used.

Fig. 1. Illustration of the three configurations of GAA FETs used in this work. Surface orientation and channel directions are denoted. Case 3 differs by having a tall cross-sectional shape. EOT = 0.8 nm is used, and ohmic contacts are used for the source/drain electrodes.

The sidewall surface orientation depends on the channel direction. Cases 2 and 3 have the same surface orientations but have different top/bottom-to-sidewall areal ratios. Case 2 has a wide cross-sectional shape with a width of 30 nm and a height of 10 nm, while Case 3 has a tall channel with width and height of 10 nm and 30 nm, respectively. The dominant channel surfaces are the top/bottom for Cases 1 and 2, while it is the sidewalls for Case 3. Table 1 shows the combinations of surface orientation, channel direction, and cross-sectional shapes.

2. Physical Models

For stress conditions, uniaxial tensile and compressive strain were applied up to ±2 %. The direction of the applied stress is parallel to the channel direction. For the strain models, a multi-valley analytical k ×p band structure and deformation potentials are used. Degeneracy of the bands are lifted by uniaxial strain, and strain-dependent effective mass and density-of-states are captured through occupancy-weighted band minima parameters. Quantum effects are also considered to capture the quantization of energy levels due to spatial confinement and selfconsistent confined carrier distributions.

3. Model Verification

Transport model parameters, i.e. fitting parameters for phonon and surface roughness scattering, for different surface orientations were calibrated to match the electron mobility of experimental results^[9,10]. Then, we compare the mobility enhancement factor ($\mu_{strained}$/$\mu_{unstrained}$) due to uniaxial tensile stress with that in the literature. Table 2 juxtaposes the results from Ref. [11]^[11] and that of this work. The stress-dependent electron mobility values are in good agreement for three different surface orientation/direction combinations at two different stress values.

1. Strain Effectiveness of GAA FETs

Due to strain, two main differences in current-voltage ($I_{D^{-}} V_{G S}$) characteristics are manifested: threshold voltage shift ($\Delta V_{t h}$) and change in drive current. Both have a significant implications to the system, where the $V_{t h}$ affects the off-state power consumption while the drive current directly affects the device and circuit performance.

Fig. 2 shows the $\Delta V_{t h}$ of GAA FETs as a function of strain. For both compressive and tensile strain conditions, the $V_{t h}$ shifts in the negative direction. Uniaxial strain lifts the energy degeneracy of the band minima valleys. The increase (or decrease) of the valley energies depend on deformation potentials, crystal orientation, channel direction, tensile/compressive, and stress amount. As some valley energies are increased, others are decreased which generally leads to a decrease in the band gap due to the lowered valley energies. Previous analytical work show the strain-dependent $\Delta V_{t h}$ can be expressed by the following expression^[12,13]:

Fig. 2. Threshold voltage shift due to compressive and tensile strain obtained (a) via simulation (this work), (b) analytical expression given by Eq. (1)^[12].

where m is body effect coefficient, $N_{v}$ is the effective density of states in the valence band, and e is the strain amount. Eq. (1) suggests that although present, the $\Delta V_{t h}$ due to strain-induced change in density-of-states or mobility ($\mu_{e}$) are minimal. Fig. 2 shows that the $\Delta V_{t h}$ result obtained by using Eq. (1) agree with that from the simulation for various strain values.

Fig. 3 shows the variation in drive current ($I_{O N}$) as a function of the applied strain. Since electrons redistribute to increase the occupancy of lower energy valleys, strain conditions can be optimized to reduce the valleyaveraged effective mass. Furthermore, due to the energy split, inter-valley scattering is reduced^[14]. Fig. 3(a) includes the effect of both $\Delta V_{t h}$ and $\Delta \mu_{e}$, while Fig. 3(b) excludes $\Delta V_{t h}$ effect and solely shows the transport aspect as the $I_{off}$ is fixed for all devices. For Case 1, the average effective mass saturates to the transverse effective mass ($m_{t}$ = 0.19 $m_{0}$) as the occupancy of ellipsoidal conduction band valleys with $m_{t}$ dominates. Hence, the mobility saturates at strain values larger than 1%. On the other hand, for Cases 2 and 3, the total effective mass in the transport direction continues to increase due to the band warping via shear strain and reduction of $m_{t}$ in the direction parallel to the applied strain^[15]. As a result, the mobility of GAA devices of Case 2 and 3 exceed that of Case 1 at high strain values, and hence exhibit higher drive current. As for the differences between Cases 2 and 3, the smaller top/bottom-to-sidewall areal ratio provides a slight advantage for Case 3 devices in the tensile strain range.

Fig. 3. Drive current of devices with different configurations, with from compressive -2% to tensile 2% uniaxial strain. All drive currents are normalized to the unstrained GAA device of Case 1. Two scenarios are shown (a) $I_{off}$ is fixed only for the unstrained cases, so the strain-dependent $\Delta V_{t h}$ is accounted in the current values, (b) $I_{off}$ is fixed at 100 nA/μm for all devices, to ignore $\Delta V_{t h}$ effects and show only the influence of the straindependent mobility.

2. Impact of GAA Device Width

Previous studies have shown wide nanosheet structures that fully utilize the device footprint and maximize the effective width $W_{eff}$^[1,2]. In this section, we highlight the importance of the nanosheet width for a given device footprint. As in the case of FinFETs, multiple GAA FETs can be placed provided that the specified device footprint is sufficiently wide. Fig. 4 shows a cross-sectional diagram of multiple devices, and the notations used for this work. Only the width of the device footprint (FW) and the cross-sectional width of the nanosheet (W_NS) are varied. The device-to-device spacing (S) is expressed as S = [FW – (N × W_NS)] / (N - 1), where N is the number of GAA FETs, and is fixed at 10 nm^[16,17]. Hence, _NS of the GAA FET determines how many devices can fit in the FW. To investigate the quantized nature of the drive current ($I_{ON}$) of GAA FETs, we compare the $I_{ON}$ for a given FW of uniaxially-tensilestrained GAA FETs with various different W_NS and FW. W_NS of 10, 20, and 40 nm are used based on recent experimental studies^[3]. Device dimensions and conditions are taken from 7 nm technology of the IRDS: $L_{G}$ = 14 nm, $V_{DD}$ = 0.7 V, $I_{OFF}$ = 100 nA/μm. To compare the intrinsic device performance, external series resistance effects are not included.

Fig. 4. Schematic diagram of multiple GAA FETs within a given device footprint (FW). Cross-sectional width (W_NS) and height (H_NS), spacing (S) are denoted.

Fig. 5 shows the $I_{ON}$ for GAA devices with a channel direction of < 100 > and < 110 > , under tensile strain values of 0, 1, and 2 %. Single-stack GAA FETs are used to focus on the effect of strain and choice of W_NS, since gains in drive current of multi-layered GAA do not directly translate to increase in circuit speed due to worse parasitic capacitance. The solid line indicates the NMOS drive current requirement, based on the IRDS^[7]. Fig. 5 shows that depending on the W_NS and FW, devices may or may not meet the $I_{ON}$ requirement. Choice of device width is crucial in maximizing the effective width of the GAA device for a given footprint. In most cases, $I_{ON}$ is higher for larger W_NS devices, but in terms of layout design flexibility smaller W_NS devices are preferable. Strain boosts the $I_{ON}$ of a single-stack GAA device without suffering from a trade-off with increased parasitic capacitance. The < 110 > channel direction has a larger current than the < 100 > direction at higher strain values ($\varepsilon$ = 2%), since the mobility saturates for the < 100 > direction devices.

Fig. 5. GAA NMOS drive current $I_{ON}$ against the device footprint width (FW). Device conditions are $L_{G}$ = 14 nm, $V_{DD}$ = 0.7 V, $I_{OFF}$ = 100 nA/μm (a)-(c) Surface orientation/channel direction of (001) / < 100 > , (d)-(f) (001)/ < 110 > . Solid line is the specification from the IRDS^[8]. FW = 10 nm is denoted by a dotted line.