Mobile QR Code QR CODE

REFERENCES

1 
Loubet N., et al , June 2017, Stacked nanosheet gate-allaround transistor to enable scaling beyond finFET, in Proc. Symp. VLSI Technol., pp. 230-231DOI
2 
Mertens H., et al , Dec. 2017, Vertically stacked gate-allaround Si nanowire transistors : key process optimizations and ring oscillator demonstration, in IEDM Tech. Dig., pp. 828-831DOI
3 
Zhang J., et al , Dec. 2017, High-k Metal Gate Fundamental Learning and Multi-VT Options for Stacked Nanosheet Gate-All-Around Transistor, in IEDM Tech. Dig., pp. 537-540DOI
4 
Barraud S., et al , June 2017, Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain, in IEDM Tech. Dig., pp. 464-647DOI
5 
Elmessary M. A., et al , Sep. 2017, Study of Strained Effects in Nanoscale GAA Nanowire FETs Using 3D Monte Carlo Simulations, in ESSDERC, pp. 184-187DOI
6 
Al-Ameri T., et al , Sep. 2016, Impact of strain on the performance of Si nanowires transistors at the scaling limit: a 3D Monte Carlo / 2D Poisson Schrodinger simulation study, in SISPAD, pp. 213-216DOI
7 
International roadmap for devices and systems, 2016 edition, https://irds.ieee.org/reportsGoogle Search
8 
Sentaurus Device, version M-2016.12, Synopsys, Inc., Mountain View, CA, USAGoogle Search
9 
Mujtaba S. A., et al , 1994, Semi-empirical local NMOS mobility model for 2-D device simulation incorporating screened minority impurity scattering, in Proc. 5th Intl. Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits (NUPAD), pp. 3-6DOI
10 
Mujtaba S. A., et al , 1995, Accurate modeling of Coulombic scattering, and its impact on scaled MOSFETs, in Proc. Symp. VLSI Technol., pp. 99-100DOI
11 
Tan Y., et al , 2008, Analytical Electron-Mobility Model for Arbitrarily Stressed Silicon, IEEE Trans. Electron Devices, Vol. 55, pp. 1386-1390DOI
12 
Kang T., 2012, Evidence for Silicon Bandgap Narrowing in Uniaxially Strained MOSFETs Subjected to Tensile and Compressive Stress, IEEE Trans. Electron Devices, Vol. 33, pp. 770-772DOI
13 
Zhang W., et al , 2008, On the Threshold Voltage of Strained-Si-Si1-xGex MOSFETs, IEEE Trans. Electron Devices, Vol. 52, pp. 263-268DOI
14 
Dhar S., et al , 2005, Electron Mobility Model for Strained-Si Devices, IEEE Trans. Electron Devices, Vol. 52, pp. 527-533DOI
15 
Uchida K., et al , Dec. 2005, Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime, in IEDM Tech. Dig., pp. 129-132DOI
16 
Barraud S., et al , Dec. 2017, Performance and Design Considerations for Gate-All-Around Stacked-NanoWires FETs, in IEDM Tech. Dig., pp. 677-680DOI
17 
Martens H., et al , Dec. 2017, Vertically Stacked Gate-All-Around Si Nanowire Transistors : Key Process Optimizations and Ring Oscillator Demonstration, in IEDM Tech. Dig., pp. 829-831DOI