1. Configuration of Transmitter Circuit

Fig. 4 shows a block diagram of a transmitter. The transmitter is composed of a D-FF that generates a modulated frame signal and PLL circuit that generates a frequency-modulated clock signal for the D-FF. Frame signals are input to the D-FF using frequency-modulated signals as the clock signals, and a modulated frame signal is generated. By modulating the frame signals in accordance with the labeling signals, the labeling-signal information is multiplexed.

Fig. 4. Block diagram of transmitter.

2. Operation Principle of Modulating Frame Signal

Fig. 5 shows the timing charts of the D-FF outputs. When the clock signal is not frequency modulated, non-modulated frame signals are output, as shown in Fig. 5(a). As shown in Fig. 5(b), however, when the frequency-modulated signal is used as the clock signal, modulated frame signals are output.

Fig. 5. Timing charts of D-FF outputs when (a) using non-modulated, (b) modulated clock signals.

Next, the effect of the phase difference of the clock signal on the D-FF is considered. The timing chart of the D-FF using the modulated clock signal is shown in Fig. 6. When the phase difference from the ideal position of the falling edge (the center of the bit) ${\Delta}$${\phi}$ is $π$ (equivalent to the half of 1-bit width) or less, the frame signal is modulated and the bit rate is changed, but the binary information of the D-FF output is the same as that of the D-FF input (original frame signal), as shown in Fig. 6(a). When the phase difference is larger than $π$, the clock signal detects the previous or next bit information of the frame signal. As a result, bit error occurs and the output data frame remain changed, as shown in Fig. 6(b). Therefore, it is necessary to set the frequency-shift amount for frequency modulation so that the phase difference will not exceed $π$.

Fig. 6. Comparison between timing charts when (a) ${\Delta}$${\phi}$ ${\leq}$ $π$, (b) ${\Delta}$${\phi}$ > $π$.

3. PLL Circuit with Variable Divider

To generate frequency-modulated clock signals, a PLL circuit with a variable divider is used as a synthesizer. Fig.~7 shows the configuration of the PLL circuit. The frequency of the VCO output, $_f{\mathrm{VCO}}$, can be written as

where $_f{\mathrm{r}}$ is the frequency of the reference signal input to an EXOR, ${N}$ is the center division ratio, and ${a}$ is the variation in the division ratio, respectively. When the ratio of the variable divider is changed, i.e., ${N}$ ${\rightarrow}$ (${N}$ + ${a}$) ${\rightarrow}$ ${N}$ ${\rightarrow}$ (${N}$ ${-}$ ${a}$) ${\rightarrow}$ ${N}$ ${\rightarrow}$ (${N}$ + ${a}$) ${\rightarrow}$${\dots}$, the frequency of the VCO output is also changed. In other words, we can modulate the clock signal by changing the division ratio.

Fig. 7. Configuration of PLL synthesizer with variable divider.

4. Modulation-control Circuit for Multiplexing Labeling Signal

The configuration of our designed modulation-control circuit is shown in Fig. 8. We designed a PLL circuit with two feedback paths. One path has a divider with a fixed ${N}$, and the other has a variable divider with ${N}$ ${\pm}$ ${a}$. Modulation or non-modulation can be selected by switching the feedback path in accordance with the labeling signal. The operation of the PLL circuit is shown below.

Fig. 8. Selecting (a) non-modulation, (b) modulation by switching feedback path.

(1) For labeling signal “0”, the feedback path with a fixed divider is selected using a SEL, and the PLL circuit oscillates at a center frequency, $_f{\mathrm{c}}$ = ${N}$ ${\times}$ $_f{\mathrm{r}}$, as shown in Fig. 8(a). Since the clock signal for the D-FF is not modulated, the D-FF outputs non-modulated frame signals.

(2) For labeling signal “1”, the feedback path with the variable divider is selected, and the PLL circuit oscillates at $_f{\mathrm{VCO}}$ = (${N}$ ${\pm}$ ${a}$) ${\times}$ $_f{\mathrm{r}}$, as shown in Fig. 8(b). Since the clock signal is modulated by changing the division ratio of the variable divider, the D-FF outputs frequency-modulated frame signals.

5. Importance of Digital Smoothing Technique

The timing chart of the PLL circuit with two feedback paths is shown in Fig. 9. When the feedback path is switched from the fixed divider path to the variable divider path, the ratio of the variable divider may be changed to (${N}$ ${\pm}$ ${a}$) in the middle of the cycle of outputting $_f{\mathrm{r}}$ from the ${1/N}$ divider, as shown in Fig. 9. In this case, the duty ratio of the EXOR output changes irregularly. Since the LPF output also change irregularly, the PLL circuit enters an asynchronous state. Consequently, the phase difference of the clock signal (VCO output) for the D-FF exceeds the phase margin, and the bit error in the output frame signal occurs. To remove this defect, the feedback path should be changed when the ratio of the variable divider is ${N}$, as indicated by the yellow regions (acceptable regions) in Fig.~10. As a result, the SEL output is switched seamlessly, and the PLL circuit can remain in the synchronous state. Therefore, it is necessary to shift the rising edge of the labeling signal to an acceptable region.

Fig. 9. Timing chart in PLL circuit with two feedback paths.

Fig. 10. Solution to prevent PLL circuit from entering asynchronous state.

We then developed a switching timing adjustment technique called “digital smoothing” for shifting the edge timing of labeling signal to the appropriate timing. The configuration of the PLL circuit with the digital smoothing technique is shown in Fig. 11. We use another D-FF for the timing adjustment and a synchronous clock having a period of $T_{\mathrm{cycle}}$. Here, $T_{\mathrm{cycle}}$ is set to

As shown in Eq. (2), the time of one cycle (${N}$ ${\rightarrow}$ (${N}$ + ${a}$) ${\rightarrow}$ ${N}$ ${\rightarrow}$ (${N}$ ${-}$ ${a}$)) in the variable divider is equal to the total time of four cycles in the fixed divider. Therefore, the phase of the variable divider output corresponds to that of the fixed divider output in the region with the division ratio of ${N}$. The timing chart of the digital smoothing technique is shown in Fig. 12. When the falling edge of the synchronous clock is adjusted to the region where the ratio of the variable divider is ${N}$, the rising edge of the labeling signal can be shifted to an acceptable region by using the D-FF and clock. Since the SEL output is switched seamlessly, the PLL circuit can remain in the synchronous state. Consequently, the digital smoothing technique can prevent bit errors in the frame signal from occurring.

Fig. 11. Configuration of PLL circuit with digital smoothing technique.

Fig. 12. Timing chart of PLL circuit with digital smoothing technique.

1. Frequency-modulation Detection

The timing chart of the modulation-detecting circuit is shown in Fig. 15. This circuit measures the high-level duration of the received frame signal. The minimum duration of the non-modulated frame signal with the bit rate $_f{\mathrm{r}}$ is ${\tau}$$_{\mathrm{r}}$ =$1/_f{\mathrm{r}}$. As the frequency of the frame signal becomes higher, the high-level duration becomes shorter. The detecting signal is set to “1” if the duration is less than $1/_f{\mathrm{r}}$; otherwise, it is set to “0”. Therefore, frequency modulation can be detected.

Fig. 15. Operation of modulation-detecting circuit.

2. Synchronization and Demodulation of Labeling Signal

The operation of the labeling-signal demodulator is shown in Fig. 16. If the detecting signal becomes high-level multiple times, the frame signal is recognized as being modulated and the demodulator output is set to “1”. If not, the frame signal is recognized as being non-modulated and the output is set to “0”. Because our designed modulation-system protocol consists of a 1-bit synchronous signal and x-bits payload. The circuit first detects the synchronous signal. Then, reading out information of the payload starts after waiting the time of 1-bit width. In other words, the demodulator does not output “1” when the synchronization signal is detected. Thus, the received modulated frame signal can be synchronized, and the labeling information can be demodulated bit by bit.

Fig. 16. Operation of labeling-signal demodulator.

1. Transmitter

We first examined the operation of the frequency modulation for frame signals. Square waves with 250 kHz (500 kb/s) were used as the frame signals. The $_f{\mathrm{r}}$, ${N}$, and ${a}$ were set to 50 kHz, 10, and 1, respectively. The measurement results of the transmitter circuit are shown in Fig. 18. When the labeling signal was “0”, the waveform of the D-FF output was almost the same as that of the input signal, as shown in Fig. 18(a). The position of the rising/falling edges of the D-FF output did not change. Conversely, when the labeling signal was “1”, the position of the edges changed in comparison with (a), as shown in Fig. 18. These results indicate that the frame signal was modulated.

Fig. 18. Waveforms of D-FF outputs (a) without modulation, (b) with modulation.

Next, we evaluated the validity of the proposed digital smoothing technique. The LPF outputs (VCO inputs) were measured when the labeling signal was shifted from “0” to “1”. The measurement results are shown in Fig. 19. When the digital smoothing technique was not used, the LPF output was not periodic, as indicated with a white circle in Fig. 19(a). This causes asynchronization of the PLL circuit since the frequency of the VCO changes irregularly. When using the smoothing technique, however, the LPF output became periodic, as indicated with a red circle in Fig. 19(b). This means that the PLL circuit can remain in a synchronous state and the output frequency changes regularly.

Fig. 19. Waveforms of PLL circuit (a) without, (b) with digital smoothing technique.

Fig. 20 shows the waveforms of the modulated frame signal. Although the square wave with duty ratio of 1:1 was input to the D-FF, the modulated frame signal without the smoothing technique was not the same as the input signal, and bit error occurred, as indicated in Fig. 20(a). By using the digital smoothing technique, bit error was prevented, as shown in Fig. 20(b). We verified that a frame signal can be modulated without changing the information of that signal by using the designed transmitter circuit.

Fig. 20. Waveforms of D-FF outputs (modulated frame signals) (a) without, (b) with digital smoothing technique.

2. Receiver

We extracted the labeling signal added to a frame signal by using the implemented receiver. The bit rate of the labeling signal and length of the payload were set to 3 kb/s and 10 bits, respectively. We first examined frequency-modulation detection in the received frame data. The measurement results are shown in Fig. 21. The detecting signal became high level when the labeling signal was “1”, and frequency modulation was accurately detected. We then examined the demodulated labeling signal. Fig. 22 shows the measured demodulator output. The 10-bit payload of the labeling signal (“0101010101”) multiplexed on the frame signal was demodulated without bit error. From this result, labeling signal transmission was achieved by using the implemented transceiver based on the designed modulation-system protocol.

Fig. 21. Waveforms of modulation-detecting circuit.

Fig. 22. Waveforms of binary data DEMOD.