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“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

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  4. 10.5573/JSTS.2019.19.3.276
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REFERENCES

1 
Feb. 2017, Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update, 2016-2021, Cisco White PaperGoogle Search
2 
Alwayn V., 2004, Optical Network Design and Implementation., Cisco PressGoogle Search
3 
Keiser G., 2010, Optical Fiber Communications, 4th ed., McGraw-HillGoogle Search
4 
Chiang P. C., Hung H. W., Chu H. Y., Chen G. S., Lee J., Feb. 2014, 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS, Solid-State Circuits Conference, 2014, ISSCC 2014, IEEE International, pp. 42-43DOI
5 
Bassi M., Radice F., Bruccoleri M., Erba S., Mazzanti A., Jan 2016, A 45Gb/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOI, Solid-State Circuits Conference, 2016, ISSCC 2016, IEEE International, pp. 66-67DOI
6 
Kikuchi K., Jan. 2016, Fundamentals of coherent optical fiber communications, Lightwave Technology, Journal of, Vol. 34, No. 1, pp. 157-179DOI
7 
IEEE P802.3bs, 200 Gb/s and 400 Gb/s Ethernet Task Force Home Page, http://www.ieee802.org/3/bs/Google Search
8 
Dec., 2017, IEEE standard for Ethernet, IEEE Std 802.3bs-2017Google Search
9 
Luo J., Dorren H. J. S., Calabretta N., Aug., 2012, Optical RF tone in-band labeling for large-scale and low-latency optical packet switches, Lightwave Technology, Journal of, Vol. 30, No. 16, pp. 2637-2645DOI
10 
Borzycki K., Jun., 2003, Labeling of signals in transparent optical networks, Transparent Optical Networks, 2003, ICTON 2003, 5th International Conference on, Vol. 2, pp. 166-169DOI
11 
Borzycki K., 2004, Labeling of signals in optical networks and its applications, Telecommunications and Information Technology, Journal of, Vol. 2, pp. 73-88Google Search
12 
Sato K., Shinbashi M., Taniguchi A., Wakabayashi T., 1999, SONET/SDH optical transmission system, Fujitsu Scientific and Technical Journal, Vol. 35, pp. 13-24Google Search
13 
2006, Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks, ITU-T Recommendation G.783Google Search
14 
Seifert R., 1998, Gigabit Ethernet: Technology and Applications for High-Speed LANs., Addison-WesleyGoogle Search
15 
2016, IEEE standard for Ethernet, IEEE Std 802.3-2015Google Search
16 
Omoto D., Kishine K., Inaba H., Tanaka T., 2016, Simple routing control system for 10 Gb/s data transmission using a frequency modulation technique, Smart Processing and Computing, IEIE Transactions on, Vol. 5, pp. 199-206Google Search
17 
Koda N., Furuichi K., Uemura H., Inaba H., Kishine K., Oct., 2016, Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system, SoC Design Conference, 2016, ISOCC 2016, 13th International, pp. 249-250DOI
18 
Koda N., Furuichi K., Uemura H., Inaba H., Kishine K., 2017, Simple and low power highly sensitive frequency demodulator circuit for 10-Gb/s transmission system for labeling signal, Semiconductor Technology and Science, Journal of, Vol. 17, pp. 733-741Google Search
19 
Uemura H., Furuichi K., Koda N., Inaba H., Kishine K., 2018, 10-Gb/s data frame generation circuit with frequency modulation in 65-nm CMOS, Semiconductor Technology and Science, Journal of, Vol. 18, pp. 238-245DOI
20 
Kishine K., Fujimoto K., Kusanagi S., Ichino H., May., 2004, PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits, Solid-State Circuits, IEEE Journal of, Vol. 39, No. 5, pp. 740-750DOI
21 
Kishine K., Inoue H., Inaba H., Nakamura M., Tsuchiya A., Onodera H., Katsurai H., Jun 2014, A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops, Circuits and Systems, 2014, ISCAS 2014, IEEE International Symposium on, pp. 2704-2707DOI
22 
Kishine K., Inaba H., Inoue H., Nakamura M., Tsuchiya A., Katsurai H., Onodera H., May, 2015, A multi-rate burst-mode CDR using a GVCO with symmetric loops for instantaneous phase locking in 65-nm CMOS, Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on, Vol. 62, No. 5, pp. 1288-1295DOI
23 
Kishine K., Inoue H., Furuichi K., Koda N., Uemura H., Inaba H., Nakamura M., Tsuchiya A., Oct 2016, 36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector, SoC Design Conference, 2016, ISOCC 2016, 13th International, pp. 61-62DOI
24 
Tanaka T., Furuichi K., Uemura H., Noguchi R., Koda N., Arauchi K., Omoto D., Inaba H., Kishine K., Nakano S., Nogawa M., Nosaka H., May, 2017, 25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS, Circuits and Systems, 2017, ISCAS 2017, IEEE International Symposium on, pp. 1696-1699DOI
25 
Noguchi R., Furuichi K., Uemura H., Inoue T., Tsuchiya A., Kishine K., Katsurai H., Nakano S., Nosaka H., Apr., 2018, A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS, VLSI Design, Automation and Test, 2018, VLSI-DAT 2018, International Symposium onDOI
26 
Nomura K., Koda N., Inoue T., Tsuchiya A., Kishine K., Nov., 2017, FPGA-based transceiver circuit for labeling signal transmission system, SoC Design Conference, 2017, ISOCC 2017, 14th International, pp. 310-311DOI
27 
Razavi B., 1996, Monolithic Phase-Locked Loops and Clock Recovery Circuits:Theory and Design., Wiley-IEEE PressGoogle Search
28 
Kroupa V., 2003, Phase Lock Loops and Frequency Synthesis., WileyGoogle Search
29 
Lee T., 2004, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd ed., Cambridge University PressGoogle Search
30 
Gardner F., 2005, Phaselock Techniques, 3rd ed., WileyGoogle Search
31 
Best R. E., 2007, Phase-locked loops : design, simulation, and applications, 6th ed., McGraw-HillGoogle Search
32 
Noguchi R., Imajo A., Inoue T., Tsuchiya A., Kishine K., Dec., 2018, A 25-Gb/s low-power clock and data recovery with an active-stabilizing CML-CMOS conversion, Electronics Circuits and Systems, 2018, ICECS 2018, 25th IEEE International Conference on, pp. 49-52DOI
33 
Verbist J., Verplaetse M., Srinivasan S. A., Heyn P. D., Keulenaer T. D., Vaernewyck R., Pierco R., Vyncke A., Verheyen P., Balakrishnan S., Lepage G., Pantouvaki M., Absil P., Yin X., Roelkens G., Torfs G., Campenhout J. V., Bauwelinck J., Jun., 2017, Real-time 100 Gb/s NRZ-OOK transmission with a silicon photonics GeSi electro-absorption modulator, Optical Interconnects Conference, 2017, OI 2017, 6th IEEE International, pp. 29-30DOI