1. TLP Measurement

The proposed protection device was fabricated using the 0.18-um BCD process. The basic electrical characteristics were measured by TLP and are typically presented as a plot of the current versus the voltage (I-V), showing the turn-on point parameter (Vt1, It1) of the snapback protection structure. In addition, the TLP I-V curve can easily reveal the on-resistance and the second breakdown current ⁽⁸⁾. The changes in holding voltage according to the length of the floating N+ diffusion region were measured. In order to further verify the changes in holding voltage due to the reduced current gain of the parasitic PNP bipolar transistor produced from the floating N+ diffusion region, the changes in the holding voltage were measured by increasing the floating N+ diffusion region by varying the base width, which affects the current gain in fixed conditions. Fig. 3 shows the I-V characteristics of the three most common ESD protection devices. Since the SCR has a low holding voltage of 1.5 V, latch-up problems can occur. The GGNMOS has low trigger and holding voltages, therefore, it is not suitable for high-voltage protection. On the other hand, the LIGBT can handle ESD currents effectively by operating two bipolar transistors like the SCR. Moreover, the LIGBT also operates at relatively high voltages and it can be used for higher voltage applications compared to the GGNMOS and the SCR. Fig. 4 shows the TLP I-V graph for the proposed protection device with respect to the floating N+ diffusion region L1 parameter varying from 0 um (conventional) to 4 um, 6 um, and 8 um.

Fig. 3. TLP characteristics of conventional structures (SCR, GGNMOS and LIGBT)

Fig. 4. TLP characteristics of proposed protection device with respect to the L1 parameter

Fig. 5. Respect to the L1 parameter of Triggering voltage, Holding voltage and Second breakdown current.

The measurement results showed that as width of the floating N+ diffusion region was increased from 0 um to 4 um, 6 um, and 8 um, the trigger voltage was 19.1 V, 19.4 V, 19.6 V, and 20.2 V, respectively. This shows a trigger voltage spread of approximately 1.1 V, which is almost no change. However, it can be observed that the holding voltage was 7.5 V, 8.7 V, 14.7 V, and 16.2 V, respectively, with wide increments. Fig. 5 shows the electrical characteristics (trigger voltage, holding voltage, second breakdown current) with respect to the changes in the floating N+ diffusion region. In Fig. 5, it can be observed that the second breakdown current decreases as the L1 variation. This is due to the increase in the holding voltage significantly increasing the internal resistance of the protection device. When the protection device internal resistance increases, self-heating of the device occurs during ESD current discharge, resulting in severe thermal damage of the device. Accordingly, the second breakdown current decreases as L1.

2. Transient Latch-up Test

In order to accurately test for latch-up immunity, the transient-induced latch-up (TLU) was measured. Fig. 6 shows the typical TLU measurement set-up ⁽⁹⁾. To test the LIGBT ESD protection device (DUT), anode and cathode terminals were fabricated. An ESD pulse was simulated by using a capacitor charged with constant voltage connected to the anode of the DUT as shown in Fig. 6. At the same time, the power supply that is set up for supplying DC voltage to the internal circuit is connected to the same node (node X). The ESD protection device operates if the charging voltage is applied (ESD pulse reproduced) to the capacitor through switch 1 (S1).

Fig. 6. The measurement setup for transient latch-up(TLU) test.

Here, measurements were taken by a voltage probe at node X. In addition, latch-up can be determined from changes in the DC voltage level due to the operation of the ESD protection device after the simulated ESD pulse. Fig. 7 shows the voltage waveforms obtained from TLU measurements. The results show that the holding voltages for N+ diffusion region lengths of 0 um and 4 um were 7.5 V and 8.7 V respectively, below the set-up DC power supply of 15 V. These results indicate that latch-up has occurred. It can be observed from Fig. 7(a) and (b) that the level of the DC voltage changed after ESD protection device was triggered. The device with a 6 um N+ diffusion region was also tested and a holding voltage of 14.7 V was measured. While this was close to supplied voltage of 15 V, it was also verified that latch-up occurred. In contrast, for the device with an 8 um N+ floating region, the holding voltage was 16.2 V, higher than the 15 V DC power supply, and it was observed that the supplied voltage returned to 15 V after the operation of the ESD protection device.

Fig. 7. The measured TLU voltage waveforms (a) 0 um N+ floating region occurs latch-up(fail) (b) 4 um N+ floating region occurs latch-up(fail) (c) 8 um N+ floating region passes latch-up.

Fig. 7(c) shows that the DC voltage returns to the level prior to the operation of the ESD protection device. Accordingly, the test results verify that the device has latch-up immunity. Therefore, it has been confirmed through measurements that the protection device with an N+ floating region 8 um in length can be used for the ESD protection of integrated circuits that have a 15 V power supply.

3. ESD Robustness

To evaluate the ESD sensitivity of the proposed protection device, HBM and MM pulses were applied to the device using an electrostatic discharge simulator (ESS-6008, NoiseKen Laboratory Co.) and any leakage current and changes in the DC I-V waveforms were monitored using a 370A curve tracer (Tektronix) in order to check for any device damage. The ESD robustness tests show that when the floating N+ diffusion region was 4} \textnormal{um} \textnormal{and 6} \textnormal{um}\textnormal{, the HBM protection voltage level was 8 KV and the MM protection voltage level was 800 V (maximum measurement range) while when the floating N+ diffusion region was 8 um, the HBM protection level was 6 kV and the MM protection level was 550 V (Table 1). It can be observed that the proposed protection device exceeds the commercial standard for ESD robustness (HBM=2 kV, MM=200V).

4. Temperature Characteristics

The effect of device temperature on trigger and holding voltages of the proposed protection device with L1=8 um was analyzed using the TLP measuring system and a hot-chuck controller. The high temperature characteristics are important because they affect the electrical characteristics, specially It2, of the ESD protection device ^(10-11). When the temperature of the proposed protection device was increased from 300K to 500K, the holding voltage decreased from 16.2 V to 13.5 V. Such decrease in the holding voltage is due to the decreased VBE (emitter-based voltage) of the parasitic NPN/PNP bipolar transistor at high temperatures. When the temperature increases, the diode current increases, leading to reduced VBE. The temperature dependence of the diode saturation current, which is an important factor in ESD operation, can be expressed by the following set of equations:

In Equation (1) above, as the temperature increases, VBE decreases and the holding voltage also decreases. As the carrier mobility of silicon decreases at high temperatures, its resistivity increases. Thus, the N-well resistance (RNW) and the P-well resistance (RPW) also increase as the temperature increases.

Silicon-based ESD protection devices have a 10-20% holding voltage reduction at 500k due to degradation losses ^(12-13). According to the measurement results, the proposed ESD protection device has a robustness of HBM 5kV at 400K and a holding voltage higher than the operating voltage. At a temperature of 500K, the holding voltage of the proposed ESD protection device is reduced by 16% compared to 300K.