An Byung-Kwon1
Kim Seong-Beom1
Song Yun-Heub1
-
(Department of Electronics and Engineering Hanyang Univ, Seoul, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Ovonic threshold switch, OTS, phase
change random access memory, PRAM, different
electrode bottom size, switch characteristics
I. INTRODUCTION
Phase-change Random Access Memory (PRAM) is a one of the most promising candidates
for next generation memory with non-volatility, high cycling endurance, low read/write
latency and high scalability. Phase-change Random Access Memory (PRAM) is expected
to replace the next generation of non-volatile memory and is under study. PRAM utilizes
a change in resistance value according to a phase change of a chalcogenide material.
Recently, existing memories devices are severely suffering due to scaling limits.
Industries are researching and developing to technology to overcome scaling issues.
Cross point array is structure developed to overcome scaling issues and effectively
increase high memory density. Fig. 1 shows cross point array structure. But, this structure suffers leakage issue which
is generated through unselected cell adjacent to selected cell. Therefore, the leakage
current should be reduced by using the selector device with the switching characteristic,
such as transistors, diodes, Ovonic threshold switching devices (OTS), metal insulator-transition
(MIT) devices, and mixed ionic electronic conductors (MIECs) (2). OTS can be applied more efficiently than other selectors, since OTS uses chalcogenide
materials, which is similar with PRAM. OTS utilizes a change in resistance value.
OTS on state (switch on) is low resistance value and OTS off state (switch off) is
high resistance value (1-3). It has various advantages such as high speed, process, and scaling size($<4\mathrm{F}^{2})$
(1). OTS is a one of the most promising selector. In this research, We fabricated SiTe
OTS with different width bottom electrode contact sizes and studied the differences
in the bottom electrode size I-V characteristics (4-6).
Fig. 1. Cross point array structure. (1)
II. EXPERIMENT
Fig. 2 shows device structure sectional view picture. As shown in Fig. 2, We fabricated SiTe-based OTS device for different bottom electrode contact size
structure. 18 Different bottom sizes are from 34 nm to 1921 nm and thickness is 300-nm.
Top W thickness and width are 200 nm and 60 um. Fig. 3 shows fabricated device structure bird view picture. As shown in Fig. 3, It is actually the fabricated device. The end of the device is a bottom electrode
consisting of W, consisting of 18 different sized devices and 40 identical patterns.
We measured I-V characteristics. First, read voltage (-0.2 to + 0.2 V) measured OTS
to verify uniformity of the resistance. After showing uniformity of the resistance,
18 patterns were measured with voltage (0 to 1.5 V step 0.05~V).
Fig. 2. Device Structure sectional view picture.
Fig. 3. Fabricated device Structure bird view picture.
III. RESULTS AND DISCUSSION
From the result, we verified uniformity of the resistance, result showed constant
resistance value($10^{6}$$Ω$) at 218, 420, 618, 992, 1414(nm) bottom electrode contact
size. Fig. 4 shows OTS switch characteristics. As shown in Fig. 4, OTS switch I-V characteristics is observed from 218 nm to 1414 nm size. High resistance(OTS
off) is $10^{6}$$Ω$ and Low resistance(OTS on) is $10^{3}$$Ω$, and OTS shows on/off
ratio of >$10^{3}.$ $\mathrm{V}_{\mathrm{t}}$ shows decrement with increasing size.
$\mathrm{V}_{\mathrm{t}}$ showed different values from 0.7 V to 1.4 V with different
contact size of bottom electrode, where $\mathrm{V}_{\mathrm{t}}$ decreases 0.1 V
when bottom electrode contact size increase 200 nm Table 1 is value of resistance (high/low),$\mathrm{~ V}_{\mathrm{t}}$, on/off ratio according
to OTS bottom contact size. As result, we verified OTS switch characteristics that
bottom electrode size higher between 218 nm and 1414 nm. Whenever bottom electrode
size increase by approximately 200 nm, $\mathrm{V}_{\mathrm{t}}$ decrease by approximately
0.1 V. also we verified that OTS did not show switch characteristics bottom electrode
size lower than 218 nm and higher than 1414 nm. When bottom electrode size lower than
218 nm. We thought that this phenomenon is to occur due to insufficient current flow
for OTS switch characteristics. And when bottom electrode size higher than 1414 nm,
OTS device lead to breakdown. this phenomenon is to occur due to large amount of current
to flow for OTS switch characteristics. Based on this result, it can be helpful to
manufacture the next OTS considering the thickness of OTS according to the bottom
electrode size.
Fig. 4. OTS switch characteristics (linear and log).
Table 1. Performance of OTS at bottom contact size
IV. CONCLUSIONS
In this paper, we fabricated SiTe OTS different bottom electrode contact size to study
effect of bottom electrode size on OTS. We measured OTS I-V characteristic at contact
size. Experimental results with fabricated OTS samples showed High off resistance$(10^{6}$$Ω$),
Low on resistance($10^{3}$$Ω$) and on/off ratio (>$10^{3}$). $\mathrm{V}_{\mathrm{t}}$
showed different values with different contact sizes. $\mathrm{V}_{\mathrm{t}}$
decreased 0.1 V. When bottom contact size increased 200~nm, As a result, among 18
difference bottom contact sizes between 34 nm and 1921 nm, OTS showed switching characteristic
and $\mathrm{V}_{\mathrm{t}}$ variation with between 218 nm and 1414 nm. Sized bottom
electrode samples. Based on this result, we found that the size of the bottom electrode
size greatly influences the turn on / off of the OTS during the fabrication of the
OTS and changes in the $\mathrm{V}_{\mathrm{t}}$ values by size. This results show
that the OTS is a promising selector device application for cross point array structure.
This research could will help researchers as a reference for manufacturing OTS.
ACKNOWLEDGMENTS
This research was suported by the Ministry of Trade,
Industry & Energy (MOTIE (project number 20003808)
and Korea Semiconductor Research Consortium (KSRC)
support program for the development of the future
semiconductor device.
REFERENCES
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Author
Byung-Kwon An received the B.S.
in Department of Electronics Engineering
from Kwangwoon University,
Seoul, Korea.
He is currently
pursuing the M.S degree in Department
of Electronics and Computer
Engineering from Hanyang University,
Korea.
His interests include PRAM peri circuits, PCM
device and OTS device.
Seong-Beom Kim received the B.S.
in Department of Electronics from
Hanyang University, Seoul, Korea.
He is currently pursuing the M.S.
degree in Department of Electronics
and Computer Engineering from
Hanyang University, Korea.
His
interests include PRAM peri circuits, PCM device and
OTS device.
Yun-heub Song received the B.S.
degree in electronics engineering
from Kyungpook National University,
Daegu, South Korea, in 1984, the
M.S. degree in electronics engineering
from Hanyang University,
Seoul, South Korea, in 1992 and the
Ph.D. degree in electrical engineering from Tohoku
University, Sendai, Japan in 1999.
In 1983, he was with
Samsung Electronics Corporation, Ltd., Hwasung, South
Korea, where he has been involved in process integration
for erasable programmable read-only memory.
From
1989 to 1995, he was a Technical Leader for process
integration for low-power SRAM and CPU devices.
After he received the Ph.D. degree in 1999, he rejoined
Samsung Electronics Corporation, Ltd. and worked as a
Project Manager (1999-2007) and a Vice President
(2007-2008) for the process integration and device
development for Flash memory in the Semiconductor
R&D Center.
In 2008, he joined Hanyang University as
an Associate Professor, and became a Professor of
department of Electronics and Computer Engineering,
Hanyang University in 2014.
He is the author of more
than 25 articles and more than 40 inventions. His
research interests include 3D crossbar array architecture,
selective device, switching device, MTJ reliability for
STTMRAM, 3D-Vertical NAND Flash, 3D-PCRAM
with synapse, CMOS logic device, biosensor, controlling
surface tension, etc.