1. Frequency Control Block

The FCB uses an LC-based digitally controlled oscillator (LC-DCO) to generate a 2.4-GHz band microwave signal. Fig. 6 shows the circuit schematic and output frequency range of the 8-bit LC-DCO. The resonant tank in the DCO consists of an on-chip spiral inductor and a variable capacitor that takes 8-bit digital input. The LC resonance frequency can be tuned by controlling the 8-bit digital input $\textit{FREQ[7:0]}$. In order for the FCB to stably lock to the resonance frequency of CTLR, a 2.4 GHz band LC-DCO was designed to have a tunable frequency range of 80 MHz with an 8-bit code. Additional band selection capacitors are also added to cope with nonzero frequency shifts caused by plasma ignition. The overall frequency range with additional band selection capacitors is 2.28 to 2.53 GHz. The generated microwave signal $\textit{f}$$_{DCO}$ is applied to the input of the power amplifier through a microwave selection multiplexer (MUX).

Fig. 6. (a) Circuit schematic of the 8-bit LC-DCO, (b) Output frequency range of the LC-DCO.

A digital comparator in the FCB compares the digitized reflected power $\textit{D}$$_{N}$ at the current frequency with the digitized reflected power $\textit{D}$$_{N-1}$ at the previous frequency. If $\textit{D}$$_{N}$ ${\geq}$ $\textit{D}$$_{N-1}$, the comparator output $\textit{UD1}$ = +1; if $\textit{D}$$_{N}$ < $\textit{D}$$_{N-1}$, then $\textit{UD1}$ = -1. The comparator output is applied as an input to an UP/DOWN counter to increase or decrease $\textit{FREQ[7:0]}$ by 1. The changed counter value is applied to the 8-bit variable capacitor of the LC-DCO so the output frequency is changed by (80/255) MHz. The FCB receives the new reflected power at the changed frequency and repeats the comparison process. An UP/DOWN counter acts as an integrating filter to provide the single dominant pole. Therefore, the loop of the FCB is a first-order system and unconditionally stable.

If the change in frequency causes an increase in the reflected power, the output of the comparator has the opposite sign as the previous output. As a result, the output frequency changes in the direction opposite to the previous change and moves toward to the minimum point of the reflection coefficient ($\textit{S}$$_{11}$). In the opposite case, the comparator outputs a value with the same sign, so the output frequency changes in the same direction as the previous change, and the minimum point is tracked in the same way. This simple gradient-search algorithm, makes the 8-bit LC-DCO input converge to the optimal code that minimizes the reflected power.

2. Power Regulation Block

The main function of the PRB is to provide a constant output power to the CTLR regardless of variation in the power supply or the temperature of the device. In Fig. 7, the microwave signal generated by the FCB is applied to the input of the digitally power-controllable amplifier (DPA). The microwave selection MUX determines whether to use of $\textit{f}$$_{DCO}$ or an external microwave signal $\textit{f}$$_{EXT}$, then applies the chosen microwave signal to the inverter buffer. The buffer amplifies the signal and adjusts the DC voltage level with an AC-coupling capacitor and resistors. The adjusted signal is applied to the input of a DPA that consists of 64 cascode cells. The upper NMOS gate driven is by logic gates, and determines the whether a single cascode cell is turned on or off. $\textit{ROW[0:7]}$ and $\textit{COL[0:7]}$ control the output power of the DPA by determining the number of cells that are turned on. The output terminals of the DPA bear is a choke inductor to supply DC current to the DPA and passive elements for 50-Ω matching. In Fig. 8, the measured output power of the DPA increases with increase in the number of DPA cells that are turned on. The measured maximum output power of the DPA is 19.38 dBm and the minimum output power is -20.73 dBm.

Fig. 7. Circuit schematic of the digitally power-controllable amplifier.

Fig. 8. Measured output power ($\textit{P}$$_{out}$) as a function of 6-bit input code.

The power regulation loop of the PRB operates such that the effective power $\textit{P}$$_{eff}$ (i.e., forward power minus reflected power), is equal to the target output power. The digitized effective power $\textit{D}$$_{PWR}$ is received from the digital logic block of the PDB. A digital comparator in the PRB compares $\textit{D}$$_{PWR}$ with the digitized target power $\textit{D}$$_{REF}$ value and outputs +1 or -1 ($\textit{UD2}$). An UP/DOWN counter in the PRB changes the counter value $\textit{PWR[5:0]}$ according to the $\textit{UD2}$ value, then $\textit{PWR[5:0]}$ is converted to $\textit{ROW[0:7]}$ and $\textit{COL[0:7]}$ values by a ROW/COL decoder. While the loop is active, the plasma output of the CTLR is regulated.

3. Power Detection Block

Operation of the FCB and PRB requires the reflected power and effective power of the CTLR. The PDB receives forward and reflected signals as input, then transfers the digitized reflected power to the FCB and the digitized $\textit{P}$$_{eff}$ to the PRB. The power detector shown in Fig. 9 is the front-end circuit of the PRB. Two directional couplers outside the IC sample the signal at the CTLR: one samples the forward power $\textit{P}$$_{FOR}$ and one samples the reflected power $\textit{P}$$_{REF}$; then the couplers apply these powers to the power detector. The input ports of the power detector are matched to 50 Ω; AC coupling capacitors and resistors adjust the DC voltage level. As shown in Fig. 10, the measured output voltage of the power detector increases exponentially with increase in the input power at 2.4 GHz.

Fig. 9. Circuit schematic of the power detector.

Fig. 10. Measured output voltage ($V_{PD}$) as a function of input power.

The output voltage $\textit{V}$$_{PD}$ of the power detector is converted to a 10-bit digital value ($\textit{D}$$_{V}$$\textit{[9:0]}$) by an analog-to-digital converter (ADC) to reduce sensitivity to noise. Fig. 11 and 12 illustrate the block diagram and timing diagram of the implemented 10-bit ADC. For energy efficiency, the proposed system uses successive approximation architecture (SAR). An asynchronous dynamic logic block ⁽²³⁾ in the ADC receives the ADC clock from the relaxation oscillator and generates timing logics of internal blocks such as capacitor DAC and comparator. After analog input is converted, the ADC automatically enters standby state, so the total power consumption of the ADC is minimized. Fig. 13 shows simulated power detector output and corresponding ADC output when frequency changes. When the frequency is at the optimum (2.34 GHz), the power detector output voltage changes only with 0.3 mV/MHz, requiring higher resolution of ADC. To achieve a lock at the optimum within ${\pm}$5-MHz deviation, the required ADC resolution is 10-bit assuming that ADC input range is 1.8 V. The sampling rate of ADC is designed to be not more than 1 MHz which should be significantly smaller than the loop bandwidth of the frequency tracking through the external power amplifier, the CTLR and the IC. The synthesized digital logic block compares digitized forward and reflected power to compute the reflection coefficient and $\textit{P}$$_{eff}$, and transfers it to the FCB and PRB.

Fig. 11. Block diagram of the 10-bit asynchronous SAR ADC.

Fig. 12. Simplified timing diagram of the 10-bit ADC.

Fig. 13. $\textit{P}$$_{REF}$ measurement results of power detector and 10-bit ADC.

1. Plasma Jet Impedance

Generation of plasma changes the impedance of $\textit{Z}$$_{p}$ from an infinite value to a finite value, so the $\textit{S}$$_{11}$ of the CTLR changes. The input impedance $\textit{Z}$$_{in}$ at finite $\textit{Z}$$_{p}$ is ⁽²⁰⁾

and $\textit{S}$$_{11}$ of the CTLR can be theoretically calculated as

where $\textit{Z}$ $_{p}$ = $\textit{R}$$_{p}$ - j$\textit{X}$$_{p}$, $\textit{R}$$_{p}$ is resistive impedance of the plasma jet and $\textit{X}$$_{p}$ is reactive impedance of the plasma jet. By fitting the theoretically calculated reflection coefficient and the measured reflection coefficient, resistance and reactance can be estimated. In Fig. 20, CTLR reflection coefficients were measured in the frequency range from 2.3 to 2.4 GHz at forward powers of 1.0, 1.5, and 2.0 W. The reflection coefficients of the CTLR were measured using forward and reflected power measured by two directional couplers. As the power of the plasma jet increased from 1.0 W to 2.0 W, the estimated plasma impedance decreased and the reflection characteristics of the CTLR degraded. The measured plasma impedance of the plasma jet is shown in Fig. 21.

Fig. 20. Measurement result of $\textit{S}$$_{11}$ before plasma ignition and after plasma ignition with forward input power variation.

Fig. 21. Measured resistance and reactance of the plasma jet with forward input power variation.

2. Frequency Tracking

The plasma jet impedance $\textit{Z}$$_{p}$ decreased as the forward power of the resonator increased, so that the minimum point of $\textit{S}$$_{11}$ shifted to a lower frequency. When the frequency tracking mode was activated, the minimum point of $\textit{S}$$_{11}$ is searched regardless of the initial position of the frequency. Fig. 22 shows the measured DCO frequency codes before and after the plasma ignition while the frequency tracking mode was turned on. The DCO code converged to the optimal frequency code, whether the initial code was far from or near to the optimal code. After the plasma ignition, the DCO frequency code converged to the shifted optimum frequency code after the frequency-tracking operation was iterated. After the convergence, the DCO code had a ripple in the range of ${\pm}$10 from the optimal code, so the locking range of the microwave frequency was 6.5 MHz; this error is caused by power detector gain and ADC resolution limitations; it slightly reduced power efficiency but the overall power efficiency was greatly increased.

Fig. 22. Measured DCO frequency codes while frequency tracking mode is on (Dashed lines represent the optimal DCO frequency codes).

3. Power-transfer Efficiency

The power-transfer efficiency ($\textit{PT}_{eff}$), which can be calculated as

where $\textit{P}$$_{FOR}$ is forward power in the CTLR and $\textit{P}$$_{REF}$ is reflected power in the CTLR. Fig. 23 compares the $\textit{PT}_{eff}$ for two cases of frequency control: 1) frequency fixed at the initial resonance frequency of 2.36 GHz without frequency tracking, and 2) frequency adaptively tuned with the minimum point of $\textit{S}$$_{11}$ tracking loop. In case 1), the power-transfer efficiency decreased significantly as the forward input power increased. The 95.2 % power-transfer efficiency before plasma ignition decreased to 72.1 % when the forward input power was 2.0 W. In case 2), the optimal frequency was tracked according to the change of the input impedance of the CTLR, so the power-transfer efficiency was similar to the initial efficiency of 95.1 %. The measured power-transfer efficiency was 94.8, 94.4, and 92.5 % at forward power of 1.0, 1.5, and 2.0 W, respectively. The measured performance of the implemented IC is summarized in Table 1.

Fig. 23. Power-transfer efficiency from power module to CTLR with fixed frequency and frequency tracking.