Jeon Min Gyu1
Lee Kang1
Kim Sangwan2
Kim Garam3*
Kim Jang Hyun1*
-
School of Electrical Engineering, Pukyong National University, 45 Yongso-ro, Nam-gu,
Busan 48513, Korea
()
-
Department of Electronic Engineering, Sogang University, 35 Baekbeom-ro, Mapo-gu,
Seoul 04107, Korea
()
-
Department of Electronic Engineering, Myongji University, Yongin 17058, Korea
()
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Band-to-band tunneling, tunnel field-effect transistor (TFET), charge trap, tunnel barrier, sub-threshold swing (SS)
I. INTRODUCTION
For several decades, the electrical performance of metal-oxide-semiconductor field-effect
transistor (MOSFET) for low power application has been improved Fin or gate-all-around
(GAA) structure [1-6]. However, adopting these structures for MOSFET cannot make steep switching in transfer
curves, because they have a theoretical limit of 60 mV/decade subthreshold swing (SS)
due to the Boltzmann tail in the source region [7]. In order to solve this problem, tunnel FET (TFET) has been studied for eliminating
the Boltzmann tail to show under 60 mV/decade of SS [8-16]. In addition to the low voltage operation problem, as MOSFET has been scaled down
to the nanoscale, the doping concentration of the MOSFET channel has been increased
to increase the gate’s control over the channel. As a result, a threshold voltage
($\textit{V}$$_{\mathrm{t}}$) change problem appears due to random variations such
as line edge roughness (LER), random dopant fluctuation (RDF), and poly/metal-grain
granularity (MGG) [17-23]. This makes it very difficult to produce integrated circuit chips with sufficient
yield guaranteed during production process. Therefore, a doping-less TFET (N-type
TFET) has been developed to control the energy band with work function (WF) to solve
low power driving problem of the device and the RDF problem caused by impurity [24-27]. However, since the device is fabricated based on WF control, it has some disadvantages.
Firstly, to form a tunnel barrier, a metal with a WF of less than 4 eV and more than
5 eV must be used, but there is a CMOS compatibility problem because WF control changes
the metal. Second, the effect of the actual WF doesn’t appear properly due to fermi-level
pinning [28,29]. Lastly, considering the work function variation (WFV) according to the metal grain,
there is no immunity on the current variation compared to the junction formed by doping
[30-32].
In this paper, we suggest a doping-less TFET that operates by forming energy band
with the charge trap of the gate insulator without using doping and WF of metal. The
gate insulator of the proposed device is composed of ONO (SiO$_{2}$-Si$_{3}$N$_{4}$-SiO$_{2}$)
triple dielectric. As electrons are trapped in the nitride of the ONO triple dielectric,
energy band between the source and the channel is formed [33]. Since the number of electrons being charged determines the current characteristics
output, it can be designed according to the electrical characteristics of the device
than the doping-less TFET in other papers. The paper consists as follows: Section
2 describes the doping-less TFET with charge trap layer structure and models used
in simulation. In section 3, the operating characteristics and electrical characteristics
of the device were described. In section 4, a band-to-band tunneling (BTBT) rate the
channel and electrical properties change in according to the thickness of the substrate
were explained.
II. SIMULATION CONDITION
The device structure of the charge trap TFET used in this simulation is shown Fig. 1. ONO dielectric layers consist of SiO$_{2}$, Si$_{3}$N$_{4}$ and SiO$_{2}$. The bottom
oxide thickness ($\textit{T}$$_{\mathrm{OXB}}$) of 1 nm, the top oxide thickness ($\textit{T}$$_{\mathrm{OXT}}$)
of 6 nm and the nitride thickness ($\textit{T}$$_{\mathrm{N}}$) of 2 nm and all the
source, drain and channel materials consist of Si and thickness is varied. And to
eliminate the impact of short channel effect (SCE), the channel length ($\textit{L}$$_{\mathrm{Channel}}$)
is set to 60 nm and gate length ($\textit{L}$$_{\mathrm{G}}$) to 140 nm [34]. It is doping-less in the tunnel barrier that forms the current. However, doping
was set in the source region to lower the contact resistance [35]. A source contact doping ($\textit{N}$$_{\mathrm{S}}$) of 5${\times}$10$^{18}$cm$^{-3}$(P-type),
drain doping ($\textit{N}$$_{\mathrm{D}}$) of 5${\times}$10$^{18}$ cm$^{-3}$ (N-type)
and Body doping ($\textit{N}$$_{\mathrm{sub}}$) of 1${\times}$10$^{15}$ cm$^{-3}$
(P-type). All the models are summarized in Table 1.
Fig. 1. Structure and parameter definitions of the doping-less tunnel field-effect transistor (TFET) with charge trap layer.
Table 1 Parameters used for TCAD simulation
|
Parameter
|
Value
|
|
Gate length ($\textit{L}$$_{\mathrm{G}}$)
Channel length ($\textit{L}$$_{\mathrm{Channel}}$)
|
140 nm
60 nm
|
|
Gate Bottom Oxide thickness ($\textit{T}$$_{\mathrm{OXB}}$)
Gate Top Oxide thickness ($\textit{T}$$_{\mathrm{OXT}}$)
Gate Nitride thickness ($\textit{T}$$_{\mathrm{N}}$)
Substrate thickness ($\textit{T}$$_{\mathrm{sub}}$)
|
1 nm
6 nm
4 nm
5 nm
|
|
Source contact doping concentration ($\textit{N}$$_{\mathrm{S}}$)
Drain doping concentration ($\textit{N}$$_{\mathrm{D}}$)
Body doping concentration ($\textit{N}$$_{\mathrm{sub}}$)
|
5${\times}$10$^{18}$ cm$^{-3}$ (P-type)
5${\times}$10$^{18}$ cm$^{-3}$ (N-type)
10$^{15}$ cm$^{-3}$ (P-type)
|
|
Gate Work Function ($\textit{W}$$_{\mathrm{FN}}$)
|
4.3 eV
|
The characteristics of the doping-less TFET with charge trap is simulated by the Synopsys
Sentaurus$^{\mathrm{TM}}$. The Shockley-Read-Hall (SRH) and dynamic nonlocal BTBT
model are used for accurate characteristic. The dynamic nonlocal BTBT model is essential,
since it can dynamically determine and calculate all tunneling paths based on the
energy band profile. In detail, the BTBT model calibrated with experimental result
Fig. 2(a). To calculate the BTBT generation rate ($\textit{G}$) per unit volume at the uniform
electric field limit, Kane’s model is used
The prefactor ($\textit{A}$) and the exponential factor ($\textit{B}$) are Kane parameters
while the $\textit{F}$ is electric field. For accurate simulation, we calibrate the
model parameters by extracting current from the fabricated planar TFET [14]. The calibrated parameters are as follows, where $\textit{F}$$_{0}$ = 1 V/m, $\textit{P}$
= 2.5 for an indirect BTBT, $\textit{A}$$_{\mathrm{Si}}$ = 4.0ⅹ10$^{14}$ cm$^{-3}$${\cdot}$s$^{-1}$
and $\textit{B}$$_{\mathrm{Si}}$ = 9.9ⅹ10$^{6}$ V/cm are the Kane parameters of Si,
and $\textit{F}$ denotes the electric field [37,38]. Then, the program rate in ONO dielectric also calibrated based on fabricated Metal-
SiO$_{2}$-Si$_{3}$N$_{4}$-SiO$_{2}$ capacitor. In the inset of Fig. 2(b) [39], the simple fabrication processes are shown. Each thickness of dielectric is same
with the proposed device. Then, the flat band shifts (${\Delta}$$\textit{V}$$_{\mathrm{FB}}$)
are extracted with various program times. And the electron tunnel mass calibrated
with ONO capacitors electron trapping rate Fig. 2(b). To calibrate electron trapping rate, electron tunnel mass is fitted with ${\Delta}$$\textit{V}$$_{\mathrm{FB}}$.
All the models are summarized in Table 2.
Table 2 Models in (TCAD) simulation
|
Definition
|
Model
|
|
Bandgap narrowing
Fermi Statistic
Phonon scattering
SRH recombination
BTBT
Electron trapping rate
|
Old slot boom
Fermi
Constant mobility
SRH/TAT
Nonlocal Band to Band
Electron tunnel mass
|
Fig. 2. (a) Fitted curve in transfer characteristics The tunnel rate is calibrated by modifying BTBT rate, (b) Fitted curve in electron trapping rate. The trapping is adjusted by modifying electron tunnel mass.
III. RESULTS AND DISCUSSION
Fig. 3(a) represents the energy band at $\textit{V}$$_{\mathrm{DS}}$ = 0.5 V when cut into
the ONO line. When program bias is applied in gate, the electrons on drain are moved
to the channel and when gate voltage is applied, the electrons are trapped to the
nitride region. After that, the electrons are trapped in nitride region. When programmed
(time = 100 s), it is found that the energy band in the nitride region has risen by
about 4 eV from initial state. And the energy band in the programmed nitride region
raises the energy band of the source. Thus, Fig. 3(b) shows the band structure at tunnel barrier when gate voltage ($\textit{V}$$_{\mathrm{GS}}$)
1.0 V is applied for device operation. When the device operating voltage is applied
to the gate, electrons in the valance band in silicon below the ONO region are tunneling
to the channel and current flows.
Fig. 4(a) shows the transfer characteristics of the charge trap TFET with various drain voltages
($\textit{V}$$_{\mathrm{DS}}$). There is no drain induced current enhancement depending
on the $\textit{V}$$_{\mathrm{DS}}$, so the short channel effect (SHE) can be excluded.
And the minimum SS is 28.59 mV/dec of $\textit{V}$$_{\mathrm{DS}}$ = 0.1 V, 29.01
mV/dec of $\textit{V}$$_{\mathrm{DS}}$ = 0.5 V and 34.62 mV/dec of $\textit{V}$$_{\mathrm{DS}}$
= 1.0 V. Thus, we found that the SS values for $\textit{V}$$_{\mathrm{DS}}$ changes
are below 60 mV/dec. In other words, the proposed device is a low power device that
can operate at a low gate bias. Fig. 4(b) shows the output characteristics of the charge trap TFET with various $\textit{V}$$_{\mathrm{GS}}$.
A super linear onset phenomenon, a typical characteristic of TFET with current suppressed
below $\textit{V}$$_{\mathrm{DS}}$ = 0.5 V, is found, which confirms that the proposed
device operates as a TFET [40,41].
In Fig. 3(b), the depletion of the channel increases at $\textit{V}$$_{\mathrm{GS}}$ = 1.0 V.
So, we confirmed the BTBT generation of the device. Fig. 5(a) shows a BTBT rate of the charge trap TFET with a 15 nm of substrate thickness ($\textit{T}$$_{\mathrm{sub}}$).
Since the proposed device is made of doping-less, as the thickness of the substrate
increases, the channel controllability of the gate decreases. For this reason, it
can be seen in Fig. 5 that the BTBT region from the source to the channel is pushed toward the drain. To
find out the BTBT generation rate by substrate thickness, TCAD simulation was performed
in 5 nm of $\textit{T}$$_{\mathrm{sub}}$. Fig. 5(a)-(c) shows BTBT generation rate for 15 nm, 10 nm and 5 nm of $\textit{T}$$_{\mathrm{sub}}$
respectively. The 5 nm of $\textit{T}$$_{\mathrm{sub}}$ shows high BTBT rate.
Fig. 6(a) shows the transfer characteristics of the devices with various $\textit{T}$$_{\mathrm{sub}}$
at 0.5 V of $\textit{V}$$_{\mathrm{DS}}$. Since it was not simulated with high doping,
as the $\textit{T}$$_{\mathrm{sub}}$ increases, the depletion area increases and threshold
voltage ($\textit{V}$t) increases. In detail, it can be seen that there is abrupt
improvement of on-current ($\textit{I}$$_{\mathrm{ON}}$) under 5 nm of $\textit{T}$$_{\mathrm{sub}}$.
Conversely, over 5 nm of $\textit{T}$$_{\mathrm{sub}}$, the $\textit{I}$$_{\mathrm{ON}}$
in each devices, is shown with similar level. It is because that as we mentioned above,
the tunneling region with highest BTBT rate is restricted near surface of channel
due to the gate controllability. Therefore, it is better to design the device under
5 nm of $\textit{T}$$_{\mathrm{sub}}$. Fig. 6(b) is a characteristics curve according to the number of electrons charged to nitride
that varies with the program time at 0.5 V of drain voltage ($\textit{V}$$_{\mathrm{DS}}$).
When program for a long time, as the number of electrons charged to the nitride increases,
it turns on at a low gate voltage and has a high $\textit{I}$$_{\mathrm{ON}}$ value.
When the program time is longer than 100 μs, the on-current ($\textit{I}$$_{\mathrm{ON}}$)
and $\textit{V}$$_{\mathrm{t}}$ are almost saturated. Conversely, when the program
time is short (< 20 μs), the electrons charged to the nitride are reduced, do the
channel depletion is increased and the $\textit{V}$$_{\mathrm{t}}$ is increased.
Fig. 3. Energy band diagram (a) SiO$_{2}$-Si$_{3}$N$_{4}$-SiO$_{2}$ in initial and programed, (b) tunnel barrier at $\textit{V}$$_{\mathrm{GS}}$=0 V and 1.0 V.
Fig. 4. (a) Transfer curve, (b) output characteristics of the charge trap TFET.
Fig. 5. BTBT generation rate on the source region (a) 15 nm, (b) 10 nm, (c) 5 nm of substrate thickness ($\textit{T}$$_{\mathrm{sub}}$).
Fig. 6. Transfer curve (a) for each thickness of substrate at $\textit{V}$$_{\mathrm{DS}}$ = 0.5 V, (b) by programed time that vary depending on the amount of electron charged to nitride.
Finally, the electrical characteristics of the $\textit{T}$$_{\mathrm{sub}}$ and [24,25, 27] are summarized in Table 3 The SS was extracted at 10$^{-15}$ A of drain current ($\textit{I}$$_{\mathrm{D}}$)
and 10$^{-14}$ A of $\textit{I}$$_{\mathrm{D}}$. In the case of Ref. [24], the $\textit{I}$$_{\mathrm{D}}$ cannot be measured until 10$^{-15}$ A, so it was
measured at the minimum current range as far as a decade. The $\textit{V}$$_{\mathrm{t}}$
and $\textit{I}$$_{\mathrm{ON}}$ were defined as $\textit{V}$$_{\mathrm{GS}}$ with
1.0 V-$\textit{V}$$_{\mathrm{DS}}$ at 10$^{-13}$ A-$\textit{I}$$_{\mathrm{D}}$ and
0.9V-$\textit{V}$$_{\mathrm{GS}}$, respectively. The proposed device has a lower SS
of 22.35 mV/dec than reference devices and a high $\textit{I}$$_{\mathrm{ON}}$ of
7.823ⅹ10$^{-8}$ A/μm. In the case of Ref. [24,25, 27], the ($\textit{V}$$_{\mathrm{t}}$) is in the range of 0.4~0.5 V at 1.0 V-$\textit{V}$$_{\mathrm{DS}}$.
Note that, since the reference devices are operated by forming a band with the work
function (WF) of the metal, it is difficult to adjust $\textit{V}$$_{\mathrm{t}}$
similar with that of proposed TFET. On the other hand, the proposed device has a low
$\textit{V}$$_{\mathrm{t}}$ of 0.03~0.12 V, so it can be operated at low power.
Table 3 Comparison of electrical characteristics
|
Device
|
$\textit{V}$$_{\mathrm{t}}$[V]
($\textit{I}$$_{\mathrm{D}}$ = 10$^{-13}$A/μm)
|
$\textit{I}$$_{\mathrm{ON}}$ [A/μm]
($\textit{V}$$_{\mathrm{GS}}$=0.9 V)
|
SS [mV/dec]
|
|
2 nm
|
-0.0948
|
7.823ⅹ10-8
|
22.35
|
|
5 nm
|
0.0323
|
1.805ⅹ10-8
|
34.62
|
|
10 nm
|
0.101
|
1.028ⅹ10-8
|
36.78
|
|
15 nm
|
0.120
|
9.773ⅹ10-8
|
38.34
|
|
Ref. [24]
|
0.512
|
5.542ⅹ10-8
|
64.95
|
|
Ref. [25]
|
0.455
|
4.608ⅹ10-8
|
32.28
|
|
Ref. [27]
|
0.438
|
7.137ⅹ10-8
|
25.49
|
IV. CONCLUSIONS
In this paper, we analyzed the doping-less TFET using charge trap through TCAD simulation.
In the case of a doping-less TFET using a charge trap, it forms a tunnel barrier by
adjusting the amount of charged electrons to time, so electrical characteristics can
be freely adjusted compared to the doping-less TFET using WF of metal and TFET using
doping. Despite these advantages, when the thickness of the substrate ($\textit{T}$$_{\mathrm{sub}}$)
become thicker, the gate’s control to the channel decreases, and the depletion extends
to the drain region, which reduces the BTBT rate and increases the threshold voltage
($\textit{V}$$_{\mathrm{t}}$). To investigate this phenomenon, the BTBT rate was confirmed
with various $\textit{T}$$_{\mathrm{sub}}$. As a result, when the $\textit{T}$$_{\mathrm{sub}}$
is thin, the BTBT rate is improved, and the proposed TFET shows improved current and
SS. Therefore, our proposed TFET can be attractive solution for modern scaled semiconductor
device technology with improved electrical characteristics.
ACKNOWLEDGMENTS
This work was supported by the National Research Foundation of Korea (NRF) grant
funded by the Korea government (MSIT) (No. 2020R1G1A1101263) and (NRF-2020R1G1A1007430).
The EDA tool was supported by the IC Design Education Center (IDEC), Korea.
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Min Gyu Jeon is pursuing the B.S. degree in the Department of Electrical Engineering,
Pukyong National University, Korea. His interests include TFET and GAA FET.
Kang Lee is pursuing the B.S. degree in the Department of Electrical Engineering,
Pukyong National University, Korea. His interests include TFET and Marchine Learning.
Sangwan Kim was born in Daegu, South Korea, in 1983. He received the B.S., M.S.,
and the Ph.D. degrees in Electrical Engineering from Seoul National University, Seoul,
Republic of Korea, in 2006, 2008, and 2014, respectively. He had been a post-doctoral
scholar at the Department of Electrical Engineering and Computer Sciences, University
of California, Berkeley, USA, from 2014 to 2017. He had been with the Department of
Electrical and Computer Engineering, Ajou University, Suwon, Republic of Korea, as
Assistant/Associate Professor from 2017 to 2022. Since 2022, he has been a Faculty
Member with Sogang University, Seoul, Republic of Korea, where he is currently an
Associate Professor with the Department of Electronic Engineering.
Garam Kim received the B. S. and the Ph.D. degrees in electrical engineering from
Seoul National University, Seoul, Korea, in 2008 and 2014, respectively. He worked
as a senior engineer at Samsung Electronics from 2014 to 2019. In 2019, he joined
the Department of Electronic Engineering at Myongji University, Yongin, where he is
currently an assistant professor.
Jang Hyun Kim was born in Seoul, South Korea, in 1985. He received B.S. degree
in KAIST in Daejeon in Korea, in 2007. He received the M.S., and Ph.D. degrees in
electrical engineering from Seoul National University, Seoul, Korea, in 2009, and
2016, respectively. He had worked at Hynix as a senior researcher from 2016 to 2020
at the SK Hynix, Icheon, Korea. Since 2020, he has been a Faculty Member with Pukyong
National University, Busan, Korea, where he is currently an Assistant Professor with
the School of Electrical Engineering. His interests include low-power CMOS device,
DRAM and Thin film transistor.