1. Oversampling

Oversampling is a common method of improving the SNR by reducing quantization noise. The oversampling ADC samples and quantizes the input signal at a much higher sampling rate than the signal band. Therefore, a small fraction of quantization noise falls into the signal band making it possible to filter the out-band noise as shown in Fig. 2. The reduction of quantization noise by oversampling can be quantified as Eq. (3). For better understanding, the signal-to-quantization noise ratio (SQNR) is considered rather than SNR.

where $P_{signal}$ and $P_{q,noise}$ denote signal and quantization noise power, respectively. The OSR is the ratio between the signal band ($f_{B}$) and Nyquist range ($f_{S}/2$). According to the above equation, there is only a 3-dB improvement in SQNR when OSR is doubled. Therefore, a very high OSR is required for high-resolution ADC designs, which has the effect of degrading power efficiency. To overcome this limitation, NS schemes are widely used along with oversampling.

Fig. 2. Quantization noise and noise transfer function (NTF).

2. Noise Shaping (NS)

Noise shaping is an essential technique and a basic concept of oversampling ADCs to enhance noise reduction effects. This is achieved by attenuating in-band noise through a high-pass noise transfer function (NTF) as shown in Fig. 2. The 1st-order DSM can be an example for presenting the NS mechanism.

The 1st-order DSM consists of a quantizer, a feedback DAC, and an integrator as described in Fig. 3. The quantizer digitizes analog input with feedback DAC converting this digitized data to an analog signal and subtracting from input, making residue voltage that contains quantization noise. Eq. (4) shows a transfer function including quantization noise, $Q\left(z\right)$.

If the $H\left(z\right)$ is a simple discrete-time integrator, $H\left(z\right)=z^{-1}/\left(1-z^{-1}\right),$ then $D_{OUT}\left(z\right)$ can be expressed as follows.

Eq. (5) shows a simple delay signal transfer function (STF), $z^{-1}$, and a high-pass NTF, $1-z^{-1}.$ Therefore, the SQNR including in-band noise attenuation by NTF can be expressed as Eq. (6).

Note that IBNG denotes in-band noise gain, which is $IBNG=~ \int _{0}^{f_{B}}\left(\left| NTF\left(f\right)\right| ^{2}/f_{B}\right)df$. If NTF is assumed to be $1-z^{-1}$, Eq. (6) can be approximated as follows.

Eq. (7) shows that the SQNR increases 9-dB when OSR is doubled. Fig. 4 compares the SQNR improvement between oversampling with and without NS.

Fig. 3. (a) Block diagram of the 1st-order DSM; (b) signal flow diagram.

Fig. 4. SQNR improvement by oversampling with and without NS.

3. Noise-shaping (NS) SAR ADCs

NS-SAR ADCs have been proposed as a means to overcome the shortcomings of DSM ADCs while obtaining similar NS characteristics ^[1]. The proposed architecture replaces a quantizer and a feedback DAC of CIFF-DSM as a SAR ADC as shown in Fig. 5(a). And it realizes the NS using a finite-impulse-response and infinite-impulse-response (FIR-IIR) loop filter. The switched-capacitor FIR filter samples the residue and IIR filter integrates this residue. The signal-flow diagram including the FIR-IIR loop filter can be modeled as in Fig. 5(b). Therefore, the overall transfer function is given by Eq. (7).

Even though ^[1] achieves a sharp NTF as shown in Fig. 6, the SNDR is limited due to additional noise generated by the FIR-IIR filter. Furthermore, a power-consuming amplifier is still required. To overcome these limitations, various noise reduction techniques have been proposed. In this paper, the NS-SAR ADCs are classified into active and passive topologies based on the loop filter implementations, which are reviewed in more detail in the following section.

Fig. 5. (a) Block diagram of NS-SAR ADC; (b) signal flow diagram[1].

Fig. 6. NTF comparison between NS-SAR[1]and 1st-order DSM ADC.

1. Active Loop Filter

Active loop filters show flexible and sharp NTF because the amplifier provides sufficient gain. However, the active amplifier consumes large amounts of power which degrades the efficiency of NS-SAR. Therefore, much effort has been expended in a bid to reduce the power consumption of active strategies.

As discussed in the previous section, the first implementation of NS-SAR ADC is an active strategy using the FIR-IIR loop filter proposed in ^[1]. The switched-capacitor FIR filter and the active-amplifier-based IIR filter samples and integrates the residue, respectively. However, the proposed architecture presents only moderate SNDR performance, even though it has sharp NTF, because the passive residue sampling introduces considerable kT/C noise, with the active amplifier also introducing more noise. Improving noise performance requires the addition of large capacitors for residue sampling, while high-gain, power-consuming amplifiers are required in the IIR filter if the additional noise is to be mitigated.

To relieve the trade-off between kT/C noise and gain loss due to charge sharing in switched-capacitor FIR filter, an input buffer, implemented as an open-loop amplifier between CDAC and residue sampling capacitor, is required ^[6] as shown in Fig. 9. Although it provides a gain of 2 alleviating kT/C noise in the FIR filter, the input buffer and active amplifier in the IIR filter together consume 37% of the total power.

In ^[10,11], the open-loop dynamic-amplifier-based FIR-IIR filter is proposed as a means of reducing these extra power consumptions. Reference ^[11] replaces the input buffer and active integrator with low power open-loop dynamic amplifiers and ^[10] proposes a gain-enhanced dynamic amplifier as the input buffer. Moreover, ^[10] greatly reduces the residue sampling capacitor, such that the active-amplifier-based IIR filter can be substituted by a simple switched-capacitor integrator as shown in Fig. 10. However, the drawback is that the open-loop dynamic amplifier is sensitive to PVT variation, which degrades the NTF and limits the NS performance. To compensate for this drawback, ^[13] proposes background calibration for dynamic amplifiers which increases design complexity.

Reference ^[25] proposes a calibration-free PVT-robust closed-loop 2-stage dynamic amplifier to simplify the design complexity of the calibration as illustrated in Fig. 11. Due to the fact that the gain of the closed-loop amplifier is set by capacitor ratios, it is robust in the presence of PVT variations. In ^[27] and ^[29], the PVT-insensitive voltage-time-voltage converter and PVT-robust source follower-based unit gain buffer for active residue processing are proposed , respectively.

Fig. 9. FIR-IIR loop filter with input buffer[6].

Fig. 10. FIR-IIR loop filter with dynamic amplifier and switched-capacitor implementation[10].

Fig. 11. PVT-robust closed-loop 2-stage dynamic amplifier[25].

2. Passive Loop Filter

A passive loop filter is a simple, PVT robust, and scaling-friendly strategy because it consists of switches and capacitors. It is more power-efficient than an active loop filter given that it does not need a power-consuming amplifier. However, the passive strategy suffers from charge sharing in switched-capacitor operation and shows mild NTF due to the insufficient gain. Therefore, many efforts have been expended on reducing the charge sharing and providing adequate gain for the passive loop filter.

The first fully passive NS-SAR ADC is proposed in ^[2]. The proposed architecture utilizes the switched-capacitor circuit for the purpose of residue sampling and integration. Residue summation is realized by a multi-input comparator as shown in Fig. 12. However, switched-capacitor residue sampling attenuates the input signal by factor of 2 while the charge sharing of residue integration degrades NTF. This architecture is improved in ^[3] to 2nd-order NS. The 2nd-order NS is realized with the application of capacitor stacking ^[43] thus achieving passive gain but this does nothing to resolve signal attenuation limitations. Reference ^[4,8] eliminates this signal attenuation and realizes sharper NTF than ^[2,3]. In addition, the relative gain between input signal and integrated residue is realized through the input transistor sizing of the multi-input comparator as shown in Fig. 13. The multi-input comparator not only provides relative gain but also realizes signal summation. However, the large extra input pair which provides relative gain also introduces additional thermal noise, while the residue sampling and integration introduce extra unshaped kT/C noise, increasing the overall noise.

To alleviate the extra thermal noise from the multi-input comparator, ^[18] proposes a passive signal-residue summation scheme as shown in Fig. 14. This architecture achieves the residue summation by serialization of CDAC and integration capacitor. Moreover, the differential residue sampling on back-to-back capacitors provides a passive gain of 2 thereby eliminating the multi-input comparator. Even so, it achieves only 2x passive gain so resulting in mild NTF while the small residue sampling capacitor introduces large kT/C noise.

In ^[23], the differential integration with split capacitor and capacitor stacking are presented as described in Fig. 15. This scheme eliminates residue sampling and provides 4x the passive gain, which obviates the need for a multi-input comparator. Therefore, it reduces the kT/C and comparator noise significantly. However, it remains difficult to increase gain because the passive gain using capacitor stacking is sensitive to parasitic capacitance.

Fig. 12. Fully passive NS-SAR ADC[2].

Fig. 13. Passive NS-SAR ADC with relative gain using multi-input comparator[4].

Fig. 14. Passive signal-residue summation with 2x passive gain using capacitor stacking[18].

Fig. 15. Passive residue integration with 4x passive gain using capacitor split and stacking[23].

1. CDAC Mismatch

The CDAC mismatch introduces additional unshaped errors which cause harmonic distortion and increase the in-band noise floor. It can be modeled as an additive noise, ε(z), in a loop filter as shown in Fig. 16. Then $D_{OUT}\left(z\right)$ can be expressed as follows.

Calibration and mismatch shaping (MS) are commonly used methods to relieve the CDAC mismatch. The first one, calibration, including both the foreground and background method, compensates for CDAC mismatch in the analog and digital domain, and thus it can cancel errors from the CDAC mismatch. Foreground calibration is more widely used than the background method due to the greater simplicity of its implementations. However, foreground calibration needs additional calibration phase interrupting normal operation of ADCs.

The second one, MS suppresses the in-band noise and distortion from CDAC mismatch. The well-known MS are the dynamic elements matching (DEM) ^[44] and data-weighted averaging (DWA) ^[45]. An element selection logic (ESL) randomizes and rotates the DAC capacitor as shown in Fig. 17. Therefore, the DEM and DWA suppresses and shapes the in-band harmonic distortion and noise, respectively. The drawbacks of these DEM-based MS methods are complexity and long delay. If higher order shaping is to be achieved, more complicated logic is required, with ESL complexity growing exponentially as CDAC resolution increases. To limit complexity of the ESL, some designs shuffle only a few MSBs, despite the continuing presence of errors from LSBs.

Another MS technique is mismatch error shaping (MES) ^[6]. Conceptually, it is similar to the NS mechanism. It captures the mismatch error and feeds it back by presetting the LSBs of CDAC before sampling. Fig. 18 illustrates the 1st-order MES operations. During the sampling phase (in Fig. 18(a)), the LSB parts are preset to hold the previous mismatch error, $z^{-1}E_{M}\left(z\right)$.

Following this, the LSB parts are reset in the conversion phase (in Fig. 18(b)) to subtract the previous error from the current error, $E_{M}\left(z\right)-z^{-1}E_{M}\left(z\right)$. Therefore, it realizes a high pass shaping of the CDAC mismatch error, $\left(1-z^{-1}\right)E_{M}\left(z\right)$. The MES is easier to implement than DEM because it does not require complex logic. However, the MES suffers input dynamic range loss due to LSB presetting.

Fig. 16. Signal flow diagram of (a) CIFF; (b) EF structures including noise from CDAC mismatch.

Fig. 17. Block diagram of a simple DEM.

Fig. 18. Block diagram of a simple MES: (a) sampling phase; (b) conversion phase.

To alleviate this loss, references ^[6,23,40] apply the DEM or DWA for the MSBs and MES for LSBs. These references can also mitigate the complexity of DEM-based implementations by applying DEM techniques to only some MSBs.

2. kT/C Noise

Sampling kT/C noise is one of the unshaped noises in NS-SAR ADCs. Even though oversampling relieves kT/C noise by OSR, the disadvantage is that increasing OSR limits the signal bandwidth. Fig. 19 shows sampling circuit and its equivalent noise modeling. The on-resistance of the sampling switch introduces the noise power spectral density (PSD) of $4kTR_{ON}$ and its equivalent noise bandwidth (ENBW) is $1/4R_{ON}C_{S}$. For a simple single-pole system, the total noise power ($\overline{v_{n}^{2}}$) can be expressed as the product of the PSD and ENBW ^[46].

Therefore, only the sampling capacitor appears in total noise power. Reference ^[46,47] propose a kT/C noise reduction scheme using feedback topology by decoupling the noise PSD and ENBW. Fig. 20(a) and (b) shows a sampling circuit with a single-stage and two-stage amplifier, respectively. They reduce total sampling noise as follows.

Note that $\gamma $ is the amplifier noise factor ^[46,47].

If the amplifier gain, $g_{m,m1}$ is large, the noises can be approximate as

It shows that the sampling noise can be adjusted by $R_{L},R_{FB},$ and $g_{m2}$ while $C_{S}$ remains constant.

References ^{[22,30,46,48]} introduce the active sampling kT/C noise canceling scheme as shown in Fig. 21. This scheme captures the noise on an additional series capacitor ($C_{N}$) which is placed between the preamplifier and the latch of the comparator. Then this noise would be canceled in the next phase. Although the additional series capacitor induces extra noise, this is attenuated by preamplifier gain. However, this noise cancellation cannot be employed directly in NS-SAR.

This is because the noise cancellation occurs inside the comparator, which causes the noise captured by $C_{N}$ to be shaped by NTF. To overcome this limitation, references ^[22,30] perform the noise cancellation in the pre-comparator feedback path as shown in Fig. 22. Although EF structure has been adopted to validate the pre-comparator kT/C noise cancellation, they can also be applied to CIFF structures. These techniques alleviate the burden of the ADC input driver by reducing the sampling capacitor.

Fig. 19. (a) Simple sampling circuit; (b) its equivalent noise modeling[46].

Fig. 20. kT/C noise reduction using feedback topology with (a) single-stage; (b) two-stage amplifier[46,47].

Fig. 21. kT/C noise cancellation using series capacitor[46,48].

Fig. 22. Pre-comparator kT/C noise cancellation[22,30].

1. Hybrid Architectures

In ^[49], the NS-SAR ADC is employed as a quantizer in continuous time (CT)-DSM ADC so as to achieve a power-efficient 3rd-order NS effect. It is implemented by means of a 1st-order CT-DSM ADC and a fully passive 2nd-order NS-SAR. Thanks to the 2nd-order NS-SAR, the overall loop filter can be simplified given that it needs only a single active amplifier to realize the 3rd-order NS effect.

In ^[50,51], the pipelined NS-SAR ADC is proposed to solve BW limitation. The 2nd-stage residue is summed with 1st-stage residue, which amplified by inter-stage residue amplifier. Then further quantized in 2nd-stage, realizing EF NS. Since the 2nd-stage integrates the residue during the 1st-stage sampling and conversion a high-speed pipeline operation is maintained.

In ^[32,39], the multi-stage noise-shaping (MASH) ADC is presented. Reference ^[32] implements NS-SAR assisted pipelined ADC, realizing 2-0 MASH. The 2nd-orer NS-SAR ADC shapes the inter-stage gain error and nonlinearities of pipelined ADC. It relaxes the gain sensitivity of conventional pipelined ADC. Reference ^[39] proposes 1-1 MASH structure using fully passive NS-SAR and VCO ADC alleviating the burden of driving large sampling capacitors. The proposed MASH ADC allows for the use of the low-resolution NS-SAR as a 1st-stage, allowing for small input capacitors while signal attenuation of passive NS-SAR is addressed by leveraging it to linearize the VCO.

2. Time-interleaved Architectures

The oversampling ADCs suffer from the limited BW due to the OSR. Time-interleaved (TI) architecture is a well-known technique for increasing BW. However, this TI strategy is not a straightforward solution for NS-SAR ADCs due to the residue process. Because the multiple channels (sub-ADCs) operate in parallel with overlapping the conversion cycles, the residue from the previous channel cannot be fed back to the adjacent channel directly as shown in Fig. 23(a). To apply the TI technique to NS-SAR ADC, ^[16] proposes the midway feedback which is multiple feedback to other channels as shown in Fig. 23(b). Thanks to the inherent delay in midway feedback, this allows high-order NTF to be realized. However, as the TI NS-SAR ADC in ^[16] is implemented on EF architecture, it requires a summing amplifier consuming large static power. Moreover, it shows mild NTF to ensure stability due to the gain of the amplifier being vulnerable to PVT variations. To overcome these drawbacks of the EF structure, ^[28,31] realizes the TI NS-SAR ADC using CIFF architecture. ^[31] uses the multi-input comparator as a feedforward summation and ^[28] adopts the passive summation using capacitor stacking scheme. Therefore, the CIFF-based TI NS-SAR ADCs show better power efficiency than EF-based structure due to unnecessariness of a static amplifier.

Fig. 23. (a) Inter-channel non-casual feedback; (b) midway feedback proposed in[16].