LeeDong-Ho1
JeongHwan-Seok1
KimYeong-Gil1
KimMyeong-Ho2
SonKyoung Seok2
LimJun Hyung2
SongSang-Hun1*
KwonHyuck-In1*
-
(School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974,
Korea)
-
(Research and Development Center, Samsung Display, Yongin 17113, Korea)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Index Terms
Indium-gallium-zinc oxide (IGZO), thin-film transistors (TFTs), quantitative analysis, channel width, self-heating stress
I. INTRODUCTION
Since the invention of indium gallium zinc oxide (IGZO) thin-film transistors (TFTs)
in 2004 by Prof. Hosono and coworkers, IGZO TFTs have attracted considerable attention
because of their superior properties including high electron mobility, excellent on/off
ratio, low process temperature, and high uniformity [1-4]. These merits render IGZO TFTs particularly suitable for applications in high-resolution
organic light emitting diode (OLED) displays [5]. To utilize IGZO TFTs for pixel and gate driver circuits in OLEDs, they should possess
high current capability because the drivers will need to handle currents of hundreds
of milliamperes on each output [6,7]. To increase the current capability of IGZO TFTs, it is necessary to increase their
channel width. Therefore, it is very important to study the effects of channel width
on the electrical stability of IGZO TFTs. Previously, some studies have been conducted
on the effects of channel width on the electrical stability of IGZO TFTs, especially
under self-heating stress (SHS) conditions [8-10]. These studies revealed that the degree of degradation was more significant under
SHS conditions in IGZO TFTs with increased channel width. This was mainly attributed
to the enhanced self-heating effects in TFTs with a wider channel width, originating
from the low thermal conductivity of the IGZO [11]. However, most of these previous studies only analyzed the self-heating effects qualitatively.
For example, the dominant degradation mechanism enhanced by the self-heating effects
was attributed to one of two mechanisms: electron/hole trapping in the gate dielectric
or changes in the subgap density of states (DOS) in the active region [12,13]. However, since several degradation mechanisms of different origins can cause stress-induced
electrical performance degradation in IGZO TFTs, it is very important to analyze degradation
caused by self-heating quantitatively in IGZO TFTs. In this study, we examined the
effects of channel width on electrical performance degradation in commercially-available
top-gate self-aligned (TG-SA) coplanar IGZO TFTs under SHS. Furthermore, we comprehensively
investigated the quantitative contribution of every degradation mechanism that caused
the SHS-induced threshold voltage shift (ΔVTH) in IGZO TFTs
with different channel widths.
II. EXPERIMENTAL DETAILS
The IGZO TFTs used in this study had a TG-SA coplanar structure and were fabricated
using the following process. First, an oxide buffer layer was deposited on a polyimide
substrate using plasma-enhanced chemical vapor deposition (PECVD). Then, an IGZO layer
(In:Ga:Zn = 1:1:1 at \%) was deposited by radio-frequency magnetron sputtering.
Subsequently, a SiOX layer was deposited by PECVD as a gate dielectric,
followed by the deposition of a gate metal (Molybdenum). After deposition and patterning
of the gate electrode and gate dielectric, SiOX and SiNX
were deposited as an interlayer dielectric (ILD) by PECVD and patterned to form via
holes. The via-contact-type n+-IGZO source (S) and drain (D) electrodes of Al
were then deposited and patterned. Finally, the devices were thermally annealed at
300 ∘C in air to achieve stable and uniform electrical performance. The fabricated
device is schematically illustrated in Fig. 1. The bias stress experiments were performed on IGZO TFTs with a width (W)/length
(L) of 30/5 μm and 50/5 μm. The electrical characterizations were conducted
using an Agilent 4156C parameter analyzer. The SHS condition used in this experiment
was a gate-to-source voltage (VGS) of 30 V, a drain-to-source voltage
(VDS) of 10 V, and a recovery condition of VGS = VDS
= 0 V at room temperature in a dark environment.
Fig. 1. Schematic illustration of fabricated TG-SA coplanar IGZO TFTs.
III. RESULTS AND DISCUSSION
Fig. 2(a) and (b) display the time dependencies of the transfer curves measured at VDS
= 0.1 V under SHS for IGZO TFTs with W/L = 30/5 and 50/5 μm, respectively, while
Fig. 2(c) and (d) respectively display the transconductances (gm = μFE⋅COX⋅VDS⋅W/L).
Here, μFE is the field-effect mobility and COX is
the gate dielectric capacitance per unit area. Fig. 2 demonstrates that the transfer curve shifted in the positive direction and gm
(and μFE) increased with increasing stress time in both TFTs.
In addition, the degree of transfer curve shift and Δgm (and
ΔμFE) were larger in the TFT with W/L = 50/5~μm.
Fig. 3(a) and (b) display the time dependencies of the transfer curves in the saturation region
(VDS = 15 V) measured from the IGZO TFT with W/L = 30/5 μm under
SHS in the forward and reverse modes, respectively, while Fig. 3(c) and (d) respectively display the dependencies of the IGZO TFT with W/L = 50/5 μm.
Here, the definitions of source and drain are the same as in the stress condition
in the forward mode, although the source and drain are interchanged in the reverse
mode. The experimental results in Fig. 3 suggest that the ΔVTH values were larger in the TFT with W/L
= 50/5 μm both operation modes, where VTH is defined in this study
as the value of VGS inducing a drain current (ID) of W/L ×
10 nA. Fig. 3 also indicates that ΔVTH extracted from the forward mode characterization
was larger than that extracted from the reverse mode characterization in both TFT
dimensions.
This result demonstrates that the local VTH exhibited different values
after SHS in both TFTs.
Fig. 4(a) and (b) display the small signal CGS-VGS and CGD-VGS
curves measured at a frequency of 50 kHz from the IGZO TFT with W/L = 30/5 μm
before and after SHS was applied for 2100 s, respectively, while Fig. 4(c) and (d) respectively display the same curves for the TFT with W/L = 50/5 μm.
Here, CGS and CGD represent the gate-to-source and gate-to-drain
capacitance obtained with a floating drain and source electrode, respectively. The
experimental results in Fig. 4 indicate that the capacitance-voltage (C-V) curves shifted in the positive direction
and stretched out after SHS in both TFTs. However, it should be stated that these
phenomena were more significant in the TFT with W/L = 50/5 μm. Fig. 4 also demonstrates that the degree the curve stretched out after SHS was more significant
in the CGD-VGS curve than in the CGD-VGS
curve in both TFTs.
The experimental results in Fig. 2-4 clearly demonstrate that the degradation in electrical performance of the fabricated
TG-SA coplanar IGZO TFT under SHS was more significant in the TFT with the wider channel
width. This result is consistent with the results from previous studies and has been
attributed to enhanced self-heating effects [13,14]. From Fig. 2-4, it is also evident that the electrical performance of the TFTs was nonuniformly
degraded along the channel length direction. This implies it is necessary to investigate
the quantitative contribution of every degradation mechanism that causes SHS-induced
ΔVTH in the source and drain sides.
The stretched out of the C-V curve observed after SHS in the fabricated IGZO TFT in
Fig. 4 indicates that the subgap DOS increased after SHS. Therefore, to conduct a quantitative
analysis of SHS-induced electrical performance degradation in IGZO TFTs with different
channel widths, we first extracted the subgap DOS from both IGZO TFTs before and after
SHS near the source and drain sides, respectively. The subgap DOS was extracted using
the optical charge pumping method [15,16], where the CGS-VGS and CGD-VGS
curves were used to extract the subgap DOS near the source and drain sides of the
IGZO TFTs, respectively. The C-V curves were measured using an LCR meter (HP4284A)
with a 50 kHz ac signal. Here, we used a 3-mW illumination source with a wavelength
corresponding to a photonic energy of 2.4 eV. Furthermore, we obtained the energy
distribution of the subgap DOS profile from the VGS-dependent capacitance data
[17,18]. Fig. 5(a) displays the energy distribution of the subgap DOS extracted from both IGZO TFTs
near the source side before and after applying SHS for 2100 s, while Fig. 5(b) displays the distribution near the drain side of the devices. The extracted subgap
DOS (g(E)) was divided into four components according to their distribution shapes
in energy level: the densities of acceptor-like tail states (gTA), acceptor-like
deep states (gDA), shallow donor states (gSD), and oxygen-related
defect states (gO) in the energy gaps of the IGZO TFTs. We modeled the
extracted subgap DOS near EC as follows:
which is denoted by the lines in Fig. 5. In Eqn. (1), E is the electron energy, NTA is the density of trap states extrapolated
to EC, kTTA is the characteristic energy of the acceptor-like states,
k is the Boltzmann constant, NDA/NSD /NO
are the Gaussian acceptor-like/donor-like/oxygen-related state densities, EDA/ESD/EO
are the Gaussian mean energies, kTDA/kTSD/kTO
are the Gaussian deviations, and EC is the conduction band minimum. Here, the
oxygen-related defect states imply the oxygen vacancies or excess oxygen-related subgap
states [19-22].
Table 1 presents the subgap DOS parameters extracted from both IGZO TFTs near the source
and drain electrodes before and after SHS. From Fig. 5 and Table 1, it is evident that gSD increased after SHS in both devices, although
the increase was more significant in the TFT with the wider channel width, especially
near the drain side. This increase in the gSD after SHS could be attributed
to hydrogen diffusion from the source/drain IGZO metallization region (n+-IGZO
region) to the IGZO channel region. Hydrogen becomes a shallow donor, generating free
electrons in ZnO-based oxide semiconductors [23,24]. Therefore, it increases gSD and facilitates the formation of a percolation
conduction path in the IGZO. Moreover, because the channel temperature increases with
an increase in channel width (due to enhanced self-heating effects), hydrogen diffusion
accelerates more with increased channel width. The higher concentration of the hydrogen
within the channel caused higher gSD and gm (and μFE)
after SHS in the IGZO TFT with the wider channel width, as observed in Fig. 5 and 2, respectively. The larger increase in the gSD near the drain
side of the TFT after SHS could be attributed to the higher channel temperature during
SHS near the drain side of the TFT. This originated from the lower electron concentration
and higher channel resistivity causing a higher level of Joule heating during SHS.
Fig. 5 and Table 1 also demonstrate that gDA only increased after SHS in the TFT with
the wider channel width (W/L = 50/5 μm), which could be ascribed to the generation
of an M-OH bond facilitated by the higher channel temperature [25-27]. The experimental results in Fig. 5 and Table 1 clearly indicate that the channel width strongly affected the local generation of
subgap states under SHS in IGZO TFTs.
Electron trapping in the gate dielectric is another phenomenon that was enhanced by
the self-heating effects under SHS. In this study, we used the subgap DOS-based ΔVTH
decomposition technique [23, 28, 29] to extract the electron trapping-induced ΔVTH
from both IGZO TFTs after SHS near the source and drain sides. From the experimental
results in Fig. 5, we assumed that the physical mechanisms responsible for ΔVTH under
SHS in the fabricated IGZO TFTs were increased gSD and gDA
in the IGZO active region and electron trapping in the fast and slow traps in the
SiOX gate dielectric. Here, the fast/slow trap implies the electronic
trap state in the gate dielectric located relatively close to/far from the interface
with a lower/higher energy barrier for detrapping.
Fig. 6(a) illustrates the decomposition scheme of ΔVTH into the contributions
of each mechanism, where tSTR and tREC are the stress
and the subsequent recovery time during an application of the subgap DOS-based ΔVTH
decomposition technique, respectively. Here, ΔVTH_SD and
ΔVTH_DA are the ΔVTH values caused
by increases in gSD and gDA, respectively, and ΔVTH_FAST and ΔVTH_SLOW are the ΔVTH
values caused by electron trapping into the fast and slow traps, respectively. As
reported, the donor-like state becomes positively charged if the Fermi level is below
it and is neutral when the trap is occupied (i.e., the Fermi level is above). However,
the acceptor-like state is neutral if the Fermi level is below it and is negatively
charged when the trap is occupied (i.e., the Fermi level is above) [30]. Therefore, ΔVTH_SD/ΔVTH_DA adopt
negative/positive values in this study and can be calculated as
Here, q is the elementary charge of an electron, tIGZO is the active
layer thickness, and EF is the Fermi level at the flat-band condition.
Fig. 6(b) and (c) display the SHS-induced ΔVTH_SD and ΔVTH_DA values extracted near the source and drain sides from IGZO TFTs with W/L
= 30/5~μm and 50/5 μm, respectively. In Fig. 6(a), VTH recovery after termination of SHS was mainly due to electron-detrapping
from the fast trap in the gate dielectric. Therefore, ΔVTH_FAST could be obtained directly by using the subgap DOS-based ΔVTH
decomposition technique schematically illustrated in Fig. 6. Then, ΔVTH_SLOW is calculated using
where ΔVTH_TOTAL is the ΔVTH value
measured from the time dependence of the transfer curve under SHS at a specific stress
time.
Fig. 7(a) and (b) display the time evolution of ΔVTH during SHS and
recovery phases extracted in the forward and reverse operation modes from the IGZO
TFTs with W/L = 30/5 μm and 50/5 μm, respectively. Figs. 7(c) and (d)
summarize the ΔVTH values originating from each degradation
mechanism after the application of SHS for 2100 s extracted near the source and drain
sides of the IGZO TFTs with W/L = 30/5 μm and 50/5 μm, respectively. Figs.
7(c) and (d) indicate that the ΔVTH values from every degradation
mechanism increased as the channel width increased. However, the increase in the ΔVTH_SLOW was the dominant reason for the more significant electrical performance
degradation of the IGZO TFT with a wider channel width. Given that the higher channel
temperature in the TFT with a wider channel width was caused by enhanced Joule heating
effects, this is consistent with the experimental results in the previous study, where
trapped electrons transferred more easily to deeper positions within the gate dielectric
by Poole-Frenkel conduction with an increase in temperature [31,32]. Figs. 7(c) and (d) also demonstrate that ΔVTH_TOTAL, ΔVTH_SLOW, and ΔVTH_FAST exhibited higher values near the
source side of the TFT. This could be attributed to the higher vertical electric fields
under SHS near the source side, even though the channel temperature was higher near
the drain side during SHS.
Table 1. Subgap DOS parameters extracted from IGZO TFTs with both dimensions (W/L = 30/5 μm and 50/5 μm) near the source and drain electrodes before and after SHS
|
Before stress
|
After stress
(W = 30 μm)
|
After stress
(W = 50 μm)
|
Electrode
|
Source
|
Drain
|
Source
|
Drain
|
Source
|
Drain
|
NTA [cm-3eV-1]
|
1.3 × 1017
|
1.3 × 1017
|
1.0 × 1017
|
1.3 × 1017
|
1.3 × 1017
|
1.3 × 1017
|
kTTA [eV]
|
0.03
|
0.03
|
0.03
|
0.03
|
0.03
|
0.03
|
NDA [cm-3eV-1]
|
5.0 × 1014
|
5.0 × 1014
|
5.0 ×1014
|
5.0 × 1014
|
1.0 × 1015
|
1.0 ×1015
|
kTDA [eV]
|
0.73
|
0.73
|
0.73
|
0.73
|
0.73
|
0.73
|
EDA [eV]
|
−0.9
|
−0.9
|
−0.9
|
−0.9
|
−0.9
|
−0.9
|
NSD [cm-3eV-1]
|
1.7 × 1016
|
1.7 × 1016
|
2.3 × 1016
|
2.5 × 1016
|
2.6 × 1016
|
2.9 × 1016
|
kTSD [eV]
|
0.2
|
0.2
|
0.2
|
0.20
|
0.2
|
0.20
|
ESD [eV]
|
−0.23
|
−0.27
|
−0.23
|
−0.27
|
−0.23
|
−0.27
|
NO [cm−3eV−1]
|
1.9 × 1014
|
3.50 × 1014
|
1.9 × 1014
|
3.50 × 1014
|
1.9 × 1014
|
3.50 × 1014
|
kTO [eV]
|
0.78
|
0.78
|
0.78
|
0.78
|
0.78
|
0.78
|
EO [eV]
|
−2.0
|
−2.0
|
−2.0
|
−2.0
|
−2.0
|
−2.0
|
Fig. 2. Time dependence of transfer curves measured at VDS = 0.1 V under SHS from IGZO TFTs with (a) W/L=30/5 μm; (b) 50/5 μm. Time dependence of the transconductance (gm = μFE⋅OX⋅VDS⋅W/L) measured at VDS = 0.1 V under SHS from IGZO TFTs with (c) W/L = 30/5 μm; (d) 50/5 μm.
Fig. 3. Time dependence of transfer curves in the saturation region (VDS = 15 V) measured from the IGZO TFT with W/L = 30/5 μm in the (a) forward; (b) reverse modes under SHS. Time dependence of transfer curves in the saturation region (VDS = 15 V) measured from the IGZO TFT with W/L = 50/5~μm in the (c) forward; (d) reverse modes under SHS.
Fig. 4. Small signal: (a) CGS-VGS; (b) CGD-VGS curves measured at a frequency of 50 kHz from the IGZO TFT with W/L = 30/5 μm before and after application of SHS for 2100 s. Small signal; (c) CGS-VGS; (d) CGD-VGS curves measured at a frequency of 50 kHz from the IGZO TFT with W/L = 50/5 μm before and after application of SHS for 2100 s.
Fig. 5. Energy distribution of the subgap DOS extracted from IGZO TFTs with W/L = 30/5 μm and 50/5 μm near the (a) source; (b) drain sides of the IGZO TFT before and after application of SHS for 2100 s.
Fig. 6. (a) Schematic illustration of the ΔVTH decomposition scheme based on the subgap DOS-based ΔVTH decomposition technique. The ΔVTH_SD and ΔVTH_DA values were extracted near the source and drain sides after applying SHS for 2100 s from IGZO TFTs with (b) W/L = 30/5 μm; (c) 50/5 μm.
Fig. 7. Time evolution of ΔVTH during SHS and recovery phases extracted during forward and reverse mode operation from IGZO TFTs with (a) W/L = 30/5 μm; (b) 50/5 μm. The ΔVTH values originated from each degradation mechanism after applying SHS for 2100 s extracted near the source and drain sides from IGZO TFTs with (a) W/L = 30/5 μm; (b) 50/5~μm.
IV. CONCLUSIONS
In this study, we conducted a quantitative analysis of the effects of channel width
on SHS-induced ΔVTH in IGZO TFTs. The analysis was conducted
using TG-SA coplanar IGZO TFTs with different channel widths (W/L = 30/5 μm
and 50/5 μm) and the SHS was applied under bias conditions of VGS
= 30 V and VDS = 10 V. By applying the subgap DOS-based ΔVTH
decomposition technique, we concluded that ΔVTH under SHS in
the fabricated IGZO TFTs was caused by increases in gSD and gDA
in the IGZO thin film and electron trapping in the fast and slow traps of the SiOX
gate dielectric. However, we also observed that every ΔVTH
originating from each degradation mechanism increased with an increase in channel
width. Moreover, we concluded that the increase in ΔVTH_SLOW
due to the higher channel temperature was the dominant reason for more significant
electrical performance degradation in the fabricated IGZO TFT with a wider channel
width after SHS.
ACKNOWLEDGMENTS
This research was supported by the Chung-Ang University Research Scholarship Grants
in 2022, Samsung Display Co., Ltd. and the National Research Foundation of Korea (NRF)
grant funded by the Korean government (MSIT) (2020R1A2B5B01001765).
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Dong-Ho Lee received the B.S degree in electronic engineering from Gachon University,
Gyeonggi-Do, South Korea, in 2020. Since 2020, He is currently pursuing the integrated
M.S., Ph.D. degrees in electrical and electronics engineering from Chung-Ang University.
His current research interest includes the reliability study of oxide thin-film transistors.
Hwan-Seok Jeong received the B.S. degree in chemistry from Dae-Jin University,
Pochen, South Korea, in 2015. He is currently pursuing the Ph.D. degree in electrical
and electronics engineering from Chung-Ang University. His current research interest
includes the fabrication and reliability study of oxide thin-film transistors.
Yeong-Gil Kim received the B.S. degree in electronic engineering from Seoul National
University of Science and Technology, Seoul, South Korea, in 2022. He is currently
pursuing the M.S. degree in electrical and electronics engineering from Chung-Ang
University. His current research interest includes the fabrication and reliability
study of oxide thin-film transistors.
Myeong-Ho Kim
Myeong-Ho Kim is a research engineer with the Research and Development Center,
Samsung Display, Yongin, South Korea.
Kyoung Seok Son
Kyoung Seok Son is a research engineer with the Research and Development Center,
Samsung Display, Yongin, South Korea.
Jun Hyung Lim
Jun Hyung Lim received the Ph.D. degree from the Department of Materials Science
and Engineering, Sungkyunkwan University, Suwon, South Korea, in 2006. He is in charge
of the oxide backplane with the Research and Development Center, Samsung Display,
Yongin, South Korea.
Sang-Hun Song received his BS degree in Electronics Engineering from Seoul National
University in 1886 and his MA and Ph.D. degrees from Princeton University in 1988
and 1997, respectively. His doctoral research studies on magneto-optical and magneto-transport
properties of the 2- dimensional carriers in strained semiconductor layers. In 1997,
he joined LG Semicon Co. Ltd. As a DRAM circuit designer. In 2001, he joined the School
of Electrical and Electronics Engineering at Chung-Ang University in Seoul, where
his now a professor. His research interests include semiconductor materials and devices,
and their applications to real world electronic systems.
Hyuck-In Kwon received the B.S., M.S., and Ph.D. degrees in electrical engineering
from Seoul National University, Seoul, South Korea, in 1999, 2001, and 2005, respectively.
From August 2004 to March 2006, he was a Research Associate with the University of
Illinois at Urbana-Champaign. In 2006, he joined the System LSI Division, Samsung
Electronics Company, South Korea, where he was a Senior Engineer with the Image Development
Team. From September 2007 to February 2010, he was with the School of Electronic Engineering,
Daegu University, as a full-time Lecturer and an Assistant Professor. Since 2010,
he has been with Chung-Ang University, Seoul, where he is currently a Professor with
the School of Electrical and Electronics Engineering. His research interests include
CMOS active pixel image sensors, oxide thin-film transistors, and silicon nanotechnologies.